苏州中晟宏芯信息有限公司--招聘DFT工程师

sonicme

Title: ASIC Senior DFT Engineer
Responsibilities:
1. Participate in SoC level DFT architecture definition.
2. Implement DFT strategy for the SoC chips, cooperating with design team
3. Implement basic DFT schemes, including scan, IP test, JTAG, Mem BIST and Logic BIST.
4. Develop the high coverage and cost effective test patterns.
5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.
6. Support other teams for DFT related problems.
Position Requirements:
1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 4+ years of DFT design experience, preferably with large SoC chips.
2. Handy experience on scan, mbist, lbist, JTAG, boundary scan, ATPG, DFT for IPs and RTL/gate simulation.
3. Experience on Power processor is a strong plus.
4. STA and RTL design experience is a strong plus.
5. ATE tester experience is a plus.
6. Must be able to communicate in both written and spoken English.
7. Good team work spirit and communication skill.


Title: ASIC DFT Engineer
Responsibilities:
1. Participate in DFT design flow buiding.
2. Implement basic DFT schemes, including scan, IP test, JTAG, Mem BIST and Logic BIST.
3.Develop the high coverage and cost effective test patterns.
4.Verify all DFT logics and test patterns with simulation and static timing analysis tool.
Position Requirements:
1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 2+ years of DFT design experience, preferably with large SoC chips.
2. Handy experience on scan, mbist, lbist, JTAG, boundary scan, ATPG, DFT for IPs and RTL/gate simulation.
3. Experience on Power processor is a strong plus.
3. STA and RTL design experience is a strong plus.
4. ATE tester experience is a plus.
6. Good team work spirit and self-motivated.


CV send to songlin.wu@powercore.com.cn