Continuous-Time Sigma-Delta ADC 2015年 博士论文

maverickrit

Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters
KTH Royal Institute of Technology, 2015

Contents
Contents xi
List of Acronyms xiv
List of Figures xvii
List of Tables xxii
1 Introduction 1
1.1 BackgroundandMotivation....................... 2
1.2 ResearchObjectives ........................... 6
1.3 ResearchContributions ......................... 7
1.3.1 ListofPublications ....................... 8
1.4 ThesisOrganization ........................... 11
2 Analog-to-Digital Conversion 13
2.1 PrinciplesofAnalog-to-DigitalConversion . . . . . . . . . . . . . . . 13
2.1.1 Sampling ............................. 13
2.1.2 Quantization ........................... 15
2.1.3 Nyquist-rateandOversamplingADCs . . . . . . . . . . . . . 18
2.2 PerformanceMetrics ........................... 21
2.2.1 StaticMetrics........................... 21
2.2.2 DynamicMetrics......................... 22
2.2.3 Figure-of-Merit.......................... 23
2.3 ADCArchitectures............................ 23
2.3.1 Two-StepADC.......................... 26
2.3.2 PipelinedADC.......................... 26
2.3.3 CyclicADC............................ 28
2.3.4 SARADC............................. 28
2.3.5 Sigma-DeltaADC ........................ 29
2.3.6 IncrementalSigma-DeltaADC ................. 32
2.3.7 Summary ............................. 35
3 Design Considerations in CT Implementation 37
3.1 AdvantagesofCTImplementation ................... 37
3.2 CTΣ∆Design:System-levelPerspective ............... 41
3.2.1 TheImpulseInvariantTransformation . . . . . . . . . . . . . 41
3.2.2 CTLoopFilterTopologies ................... 42
3.2.3 DesignProcedure......................... 44
3.3 CTΣ∆Design:CircuitNon-idealities ................. 45
3.3.1 IntegratorNonidealBehavior .................. 46
3.3.2 Noise,Linearity,andPower ................... 52
3.3.3 QuantizerandDACNonidealBehavior . . . . . . . . . . . . 53
3.3.4 Summary ............................. 56
4 Impact of DAC Schemes in CT Implementation 57
4.1 FeedbackDACSchemes ......................... 58
4.2 TheoreticalAnalysis ........................... 60
4.2.1 AmplitudeEfficiency....................... 62
4.2.2 JitterImmunity ......................... 63
4.2.3 Amplitude Efficiency versus Jitter Immunity . . . . . . . . . 64
4.2.4 ExcessLoopDelay........................ 66
4.2.5 IncrementalΣ∆Mode...................... 66
4.3 BehavioralSimulationsandDiscussions . . . . . . . . . . . . . . . . 69
4.3.1 TestCaseI:ConventionalΣ∆Mode . . . . . . . . . . . . . . 69
4.3.2 TestCaseII:IncrementalΣ∆Mode . . . . . . . . . . . . . . 71
4.4 Summary ................................. 77
5 A CT IΣ∆ ADC for Neural Recording Systems 79
5.1 ADC Specifications for Neural Recording Systems . . . . . . . . . . 80
5.2 ProposedArchitecture .......................... 82
5.2.1 OperationPrinciple ....................... 82
5.2.2 ModulatorTopology ....................... 82
5.3 DesignMethodology ........................... 84
5.4 CircuitImplementation ......................... 91
5.4.1 OpAmpsandOTAs ....................... 93
5.4.2 Mixed-signalBlocks ....................... 98
5.4.3 DigitalFilterandCombinationLogic . . . . . . . . . . . . . 100
5.5 SimulationResults ............................103
5.6 ExperimentalResults...........................106
5.7 Summary .................................114
6 A Comparative Study of CT IΣ∆ ADCs 115
6.1 State-of-the-ArtIncrementalΣ∆ADCs . . . . . . . . . . . . . . . . 115
6.1.1 Origin of IΣ∆ ADCs: First-order Architectures . . . . . . . . 116
6.1.2 Enhancement based on High-order Architectures . . . . . . . 116
6.1.3 Enhancement based on Multi-bit Architectures . . . . . . . . 117
6.1.4 Enhancement based on Hybrid Architectures . . . . . . . . . 118
6.1.5 OptimalFiltersinIΣ∆ADCs..................119
6.1.6 ExperimentalPrototypesofIΣ∆ADCs . . . . . . . . . . . . 119
6.2 CTIΣ∆ADCArchitectures.......................121
6.2.1 TheoreticalPerformance.....................123
6.3 Non-idealEffects .............................126
6.3.1 SensitivitytoNon-idealities...................126
6.3.2 BehavioralSimulationResults..................129
6.4 CircuitImplementation .........................132
6.5 ExperimentalResults...........................133
6.5.1 TestSetup ............................134
6.5.2 MeasurementResults ......................140
6.6 Summary .................................143
7 Enhancements on the Proposed CT IΣ∆ ADC 145
7.1 PipelinedCTIΣ∆ADC.........................146
7.1.1 ArchitectureAdvantages.....................146
7.1.2 MultiplexedInputSignals....................148
7.2 DesignStrategy..............................150
7.3 CaseStudy ................................154
7.4 Summary .................................157
8 Conclusions 159 Bibliography 161

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wangjin0215

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