内部推荐：Cadence招聘数字前端设计和数字前端验证

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1. Title: Lead/SeniorVerification Engineer (数字前端验证)

Location: SH/BJ

PositionDescription:

1.Deliver/implement advancedverification solutions by utilizing Cadence’s Incisive Verification productportfolio. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

1. Deep understanding on asicdesign and verification flow

2. Excellent knowledge ofadvanced verification methodology like eRM/OVM/UVM/VMM

3. Familiar with Cadence’s IncisivePlan to Closure Methodology (IPCM)

4. Proficiency in Systemverilog, System C and/or e (Specman)

5. Developing and usingVerification Components (eVC,OVC,UVC,VIP)

6. Developing and usingassertion based verification and formal analysis methods

7. Skilled in scriptinglanguage, such as Perl,C shell, Python, Makefile

8. Assessing the projectverification requirements

PositionRequirements:

Essential Qualifications:

1. BS degree with 4+ years ofapplicable experience, MS degree with 2+ years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.  

2. Essential that theindividual demonstrates strong communication, verbal and written. Requires goodcommunication skills in English.

DesirableQualifications:

1. Will have demonstratedhands-on experience and expertise with Cadence verification design tools orequivalent tools, flows and methodologies required to execute a verificationproject.

2. Will have demonstratedsuccessful completion of 3+ verification projects as an individual contributor

3. Will have DDR projectverification experience

2. Titleead/Senior Design Engineer (数字前端设计)

Location: SH/BJ

PositionDescription:

Deliver/implement DDR/HBM IP.The engineer should be able to act as a strong team member and contributor.Exercise judgment within generally defined practices and policies.

Specificduties include:

1. Proficiency in logicdesign, simulation, synthesis, STA and testing

2. Proficiency in Verilog andits simulation environment

3. Good knowledge of ICdesign

4. At least two years’experience driving complex IC development projects, excellent communicationskills and the uncanny ability to both lead and contribute in a cooperativeteam environment.

PositionRequirements:

1. Essential Qualifications:Must have BS degree with 4+ years of applicable experience, MS degree with 2+years of applicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics.

2. Essential that theindividual demonstrates strong communication, verbal and written.

Requires good communicationskills in English.

DesirableQualifications:

1. Will have demonstratedsuccessful completion of 5+ design projects as an individual contributor

2. Familiar withJEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience

此职位为内部推荐，有意请发mail到: flienlee@gmail.com