求助DFT阶段插入occ后断链问题 急急急

嗦螺蜜

问题卡在这里两天了，大侠们帮帮我吧，实在不知道哪里出了问题。同样的网表，dft插入压缩后，链能正确穿起来，在压缩后的基础上增加occ，链穿不正确。这是怎么回事啊？？

#############################

dft.tcl 配置如下：

read_ddc $ProjSynPath/db/${DesignTopName}_syn.ddc

current_design $DesignTopName
uniquify
link

#set_dont_use $DontUseCells
#becase all the scan dff in library have dont_use attribute
remove_attribute isf8l_ers_generic_core_ss1p08v125c/QDFZ* dont_use
remove_attribute isf8l_ers_generic_core_ss1p08v125c/QDFZ* dont_touch
remove_attribute isf8l_ers_generic_core_ss1p08v125c/QBDFZ* dont_use
remove_attribute isf8l_ers_generic_core_ss1p08v125c/QBDFZ* dont_touch
remove_attribute [get_lib_cells isf8l_ers_generic_core_ss1p08v125c/GCKES*] dont_use
remove_attribute [get_lib_cells isf8l_ers_generic_core_ss1p08v125c/GCKES*] dont_touch

#################################################################
#    ATE TIMING CONFIG
#################################################################
        set test_default_period                         100
        set test_default_delay                          0
        set test_default_bidir_delay                    0
        set test_default_strobe_width                   1
        set test_default_strobe                         40
  #     set test_dft_drc_ungate_clocks                  true
  #     set test_enable_dft_drc                         true
  #     set test_stil_netlist_format                    verilog
        set test_use_test_models                        true
        set test_default_scan_style                     multiplexed_flip_flop
#       set test_preset_bidi_signals                    false
  #     set test_setup_additional_clock_pulse           true
        set test_disable_enhanced_dft_drc_reporting     false
#################################################################
#    DFT SCAN CONFIG
#################################################################
        set_scan_configuration -add_lockup              true
        set_scan_configuration -clock_mixing            mix_clocks
        set_scan_configuration -create_dedicated_scan_out_ports         true
        set_scan_configuration -insert_terminal_lockup  true
        #set_scan_configuration -lockup_type latch      
        set_scan_configuration -style   multiplexed_flip_flop
#################################################################
#    DEFINE DFT NEED STATE HOLD SIGNAL
#################################################################
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/ANA1_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/ANA2_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/ANA3_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/ANA4_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/CTF_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/GPIO_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/PMU_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/BATVD_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/COS_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/TD_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/FLS_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/MEM_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/ADC_TST_MODE} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/SCAN_TST_MODE} -active_state 1
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_tstcod_det/SCAN_TST_MODE_NEG} -active_state 0
        set_dft_signal -view existing_dft -type Constant -hookup_pin {I_fullspeed_mux/O} -active_state 0
        set_dft_signal -view existing_dft -type Constant -port TEST_MODE -active_state 1
        set_dft_signal -view existing_dft -type Constant -port PAD_I_MODE0 -active_state 1
        set_dft_signal -view existing_dft -type Constant -port PAD_I_MODE1 -active_state 0
        set_dft_signal -view existing_dft -type Constant -port PAD_IO_GP28 -active_state 0

        set_dft_signal -view existing_dft -type Constant -port NV_TEST_MODE -active_state 1
        set_dft_signal -view existing_dft -type Constant -port DET_IN_0 -active_state 0
        set_dft_signal -view existing_dft -type Constant -port DET_IN_2 -active_state 0
        set_dft_signal -view existing_dft -type Constant -port DET_IN_2 -active_state 0
        set_dft_signal -view existing_dft -type Constant -port DET_IN_3 -active_state 0

set_dft_signal -view existing_dft -type Constant -port PAD_IO_GP13 -active_state 0
set_dft_signal -view existing_dft -type Constant -port PAD_IO_GP22 -active_state 0
#################################################################
#    Design SCAN SIGNAL
#################################################################

       set_dft_signal -view existing -type refclock -port PAD_IO_XIN -period 10 -timing [list 0 5]

        set_dft_signal -view existing_dft -type ScanClock -timing [list 45 65] -port {PAD_IO_GP32} -hookup_pin {I_scan_clk_mux/O}
        set_dft_signal -view existing_dft -type Reset -port PAD_IO_GP21 -hookup_pin {I_scan_rstn_mux/O} -active_state 0

        set_dft_signal -view existing_dft -type ScanEnable -port PAD_IO_GP1 -hookup_pin {I_scan_en_mux/O}
        set_dft_signal -view spec -type ScanEnable -port PAD_IO_GP1 -hookup_pin {I_scan_en_mux/O}

###############################################################

set_dft_configuration -clock_controller enable

set_dft_signal -view existing -type Oscillator -port PAD_IO_GP32
#set_dft_signal -view existing -type Oscillator -hookup_pin I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/u_sys_async_4clk_div_change/u_clk_out/O
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/sys_rst_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/pclk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_rsa_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_usb_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/por_cnt_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_trim_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_trng_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/wakeup_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_td_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/tmr_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_uart_dev_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_scim_dev_clk}
set_dft_signal -view existing -type Oscillator -hookup_pin {I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_fd_det_clk}
set_dft_signal -view spec -type pll_reset -port PAD_IO_GP3 -hookup_pin {I_reset_mux/O}
set_dft_signal -view spec -type pll_bypass -port PAD_IO_GP2 -hookup_pin {I_bypass_mux/O}

set_dft_configuration -scan enable

set_dft_configuration -scan_compression enable
set_scan_compression_configuration -minimum_compression 6

set_dft_signal -view spec -type TestMode -port PAD_IO_GP29 \
               -hookup_pin I_scan_gpio_mux12/O

set_dft_clock_controller \
        -cell_name pll_controller \
        -design snps_clk_mux \
        -pllclocks { \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/sys_rst_clk \
                    I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/sys_rst_clk \
                    I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_rsa_clk \
                    I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_usb_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/por_cnt_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_trim_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_trng_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/wakeup_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_td_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/tmr_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_uart_dev_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_scim_dev_clk \
I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/ckmu_fd_det_clk \
                } \
        -ateclocks {PAD_IO_GP32} \
        -cycles 2 -chain 1 -test_mode_port TEST_MODE
################################################################

        set_dft_drc_configuration -internal_pins enable
        set_dft_insertion_configuration -synthesis_optimization none \
                                        -preserve_design_name   true

set_scan_configuration -chain_count 3
set_scan_compression_configuration -min_power true

##################################################################
    # chain 1
        set_dft_signal -view spec -type ScanDataIn -port PAD_IO_GP4 -hookup_pin {I_scan_in_mux1/O}
        set_dft_signal -view spec -type ScanDataOut -port PAD_IO_GP7 -hookup_pin {I_scan_gpio_mux1/B}


    # chain 2
        set_dft_signal -view spec -type ScanDataIn -port PAD_IO_GP5 -hookup_pin {I_scan_in_mux2/O}
        set_dft_signal -view spec -type ScanDataOut -port PAD_IO_GP8 -hookup_pin {I_scan_gpio_mux2/B}


    # chain 3
        set_dft_signal -view spec -type ScanDataIn -port PAD_IO_GP6 -hookup_pin {I_scan_in_mux3/O}
        set_dft_signal -view spec -type ScanDataOut -port PAD_IO_GP9 -hookup_pin {I_scan_gpio_mux3/B}


##################################


log 问题点如下：

-------------------------------------------------------------------------
DRC Violations which prevent scan chain shifting
-------------------------------------------------------------------------

Error: Chain 1 blocked at DFF gate I_xa1310_core_0/I_ckmu_top/I_ckmu/u_ckmu_clock_gen/u_trng_async_4clk_change/dff31_q_reg after tracing 2417 cells. (S1-1)
Information: There are 2 other cells with the same violation. (TEST-171)

------------------------------------------------------------------------
Other Violations
-------------------------------------------------------------------------

Warning: Three-state net PAD_A_TP is not properly driven. (TEST-115)
Information: There are 77 other nets with the same violation. (TEST-289)



-------------------------------------------------------------------------
Summary of all DFT DRC violations
-------------------------------------------------------------------------

70 MODELING VIOLATIONS AND USER CONSTRAINTS PREVENTING SCAN INSERTION
    50 Cell has unknown model violations (TEST-451)
    20 Three-state cell has no enable violations (TEST-453)

251 DRC VIOLATIONS WHICH WILL PREVENT SCAN INSERTION
   158 Cell is constant 0 violations (TEST-504)
    93 Cell is constant 1 violations (TEST-505)

3 DRC VIOLATIONS WHICH PREVENT SCAN CHAIN SHIFTING
     3 Scan chain blockage violations (S1)

78 OTHER VIOLATIONS
    78 Improperly driven three-state net violations (TEST-115)

402 TOTAL VIOLATIONS

Error: Test design rule checking reported FATAL violations. (TEST-1314)
-----------------------------------------------------------------------------------------   
Sequential Cell Report:       Sequential       Core             Core                 
                               Cells            Segments         Segment Cells        
-----------------------------------------------------------------------------------------
Sequential Elements Detected:  16313              0                   0                       
Clock Gating Cells          :  810                                                      
Synchronizing Cells         :  33                                                      
Non-Scan Elements           :  0                                                        
Excluded Scan Elements      :  0                  0                   0                       
Violated Scan Elements      :  271                0                   0                       
(Traced) Scan Elements      :  12590   ( 77.2%)   0       (  0.0%)    0       (  0.0%)      
-----------------------------------------------------------------------------------------


Information: Test design rule checking completed. (TEST-123)
0

丶尘爷

楼主问题解决了吗？
我现在也遇到了这个问题，occ加入了clock_chain，然后链就block在了clock_chain里面。