DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Responsible for Graphic IP development and maintenance
- Responsible for IP level synthesis/formal check
- Work with verification engineer on IP level validation
- Work with front-end integration team and physical design team on timing closure
PREFERRED EXPERIENCE:
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering.
- Strong RTL coding and familiar with front-end design flow
- Experience on synthesis, timing analysis and formal verification.
- Good communication skills and fluent English.