在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2697|回复: 1

[求助] 小弟,最近在学习aurora核,编写verilog代码。实现MAP时报错如下:

[复制链接]
发表于 2015-4-15 10:11:40 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
   
PAD symbol "GTPD0_P" (Pad Signal = GTPD0_P)
   
DIFFAMP symbol "IBUFDS/IBUFDS" (Output Signal = GTPD0_left_i)
   Component type involved: IOB
   Site Location involved: A10
   Site Type involved: IPAD


Mapping completed.
See MAP report file "aurora_8b10b_v5_3_example_design_map.mrp" for details.
Problem encountered during the packing phase.

这是生产的RTL图

这是生产的RTL图
发表于 2021-6-28 19:55:35 | 显示全部楼层
同问~
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-17 12:43 , Processed in 0.019005 second(s), 11 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表