【NVIDIA社招】ASIC Physical Design Engineer（后端工程师）

NVHR

Hello All,

大家好，这边是NVIDIA的HR Tracy，目前我们在上海招聘Physical Design Engineer（后端工程师）的岗位，职位描述如下，如有意向者，欢迎发送简历到

tracyw@nvidia.com  QQ: 1751315121  收到简历 我会同您联系；

Sr. PHYSICAL DESIGN ENGINEER
DESCRIPTION:
A senior role in physical design for NVIDIA GPU and Mobile chips
Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification
Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention
Collaborate with RTL, DFT and Circuit designers to ensure the high quality of design implementation and optimization

MINIMUM REQUIREMENTS:  
-        BS in Engineering or Science
-        Power user of EDA  tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence (EDI/EPS) or Mentor (Olympus-SOC)
-        Experience in Clock/Power Distribution, P&R, Timing closure,  RC Extraction, and verification on 40nm, or 28nm technology
-        3+ years of experience in above areas

PREFERRED:
-        MS in Engineering or Science
-        Knowledge in 20nm or FinFET technology, circuit design, and package design
-        Experience in physical verification tools from Synopsys (ICV/Mojave) or Mentor (Calibre)
-        Proficiency in Perl, TCL and Makefile scripts

Tracy
021-61043650

QQ:1751315121