芯得职位

jj_seu

芯得职位
模拟
射频 SOC 数字
图像架构算法 @上海
简历发 hr@hi-talent.com

JOB TITLE: IC DesignEngineer(RF)

职位：IC设计工程师(射频)

JOB DESCRIPTION:

- RF/analog IC design for tuners andreceivers for multi-standard TV’s and other wireless systems

- Design and layout of IC blocks, such asLNA, mixer, VGA/PGA, LPF/BPF, VCO, crystal oscillator, PLL, ADC and DAC

- Simulation of RF and analog circuits andsystems in Spectre/SpectreRF and Matlab

- Testing and characterization of IC blocksand chips in lab, and ATE and field environments

- IC process and package evaluationincluding device modeling and PDK

QUALIFICATION:

- 2 years or above Experience in RF/analogdesign with MS or PhD in electric and electronic engineering;

- Understanding receiver architectures formulti-standard TV products and other wireless systems;

- Hands-on experiences in design of ICblocks to chip top levels in deep submicron CMOS technologies;

- Proficient with simulation tools(Spectre/SpectreRF) and oversight of layout design;

- Demonstrated ability for characterizationof block and chip performances in lab and ATE environments;

- Strong communication skills and alsoexcellence as team player.

Keyinformation:

方向一：射频前端设计，包括LNA（低噪声放大器）、Mixer（混频器）、振荡器等等

JOB TITLE: TM Manager（SOC架构方向）

职位：技术市场经理

JOB DESCRIPTION:

 Marketing survey

1. Collect and study market information,closely track industrial and competitor’s trend

2. Release market research report  

 Product study

1. Advanced technology on TelevisionSet/STB and WiFi, etc.

2. Competitor’s chip

3. Relevant industrial specifications

4. Relevant system applications

 New product definition

1. Product Requirement Definition (PRD)

2. Product Engineering Specification

QUALIFICATIONS:

Common requirement

1. Strong ability of

• learning newtechnologies fast

• analysis,planning, organization, communication and cooperation

• customerrelationship developing

2. MSEE with more than 8 years R&Dexperiences in SOC Design

3. Fluent in English reading, writing andverbal

Professionalrequirement

1. The candidate should be a senior SOCDesigner ( or System Engineer or Application Engineer) in digital TelevisionSOC field, and have a deep understanding of digital television/STB markets

2. Specializes in DTV SOC systemarchitecture and key blosks, including

▪ Digital and Anaog frond end

▪ Audeo/video codec

▪ Imagination post-processing

▪ Data and control interface such asDDR2/3, WiFi, Ethernet, HDMI, SD/MMC, I2C, SPI, UART…

▪ Advanced security

3. Familiar with

▪ Android/Linux OS as well as softwareecosystem

▪ Network protocol likeTCP/UDP/RTP/RTCP/RTSP…

▪ Multiscreen interactive protocol likeDLNA and Miracast…

4. With experience on drafting productengineering spec

JOB TITLE: Video ArchitectureEngineer

职位：视频架构工程师

JOB DESCRIPTION:

- Work in the area of video architecture,algorithm, and software development.

- Develop video/imagecompression/decompression/processing algorithm, including lossy and lossless.

- Build software models for algorithm withC/C++/SystemC, and assist with hardware design and verification.

QUALIFICATION:

- Ph. D or MS in signal processing, appliedmathematics, computer science, electronic engineering and related disciplinewith good mathematical knowledge.

- Strong experience in algorithmsdevelopment in one or some of the following signal processing technologies:digital video hardware or software development; image processing/multimediadesign; real-time and embedded system design.

- Experience in some of related fields:video compression; video decompression; image compression; image decompression,video processing, image processing, etc.

- Familiar with video codec standards suchas MPEG2 / H.264 / HEVC / VP9, etc.

- Strong software skills in C/C++/SystemC.

- Candidates with academic background orASIC design experience are a big plus to this position.

KeyWord：

Videocompression, image compression, lossless compression, video codec, video signalprocessing, image signal processing

有相关项目经验，偏算法

学校

浙江大学，北京大学，清华大学，同济大学，上海交大，复旦大学，中国科学技术大学, etc

JOB TITLE: Senior deviceEngineer

职位：高级器件工程师

Job responsibility:

- Development/Check/Retarget of SPICEModels related to all CMOS devices available in a PDK library (MOS, MOSCAP,Inductor, Capacitance, Resistor, Bip, Diode...);

- Work closely with foundry engineers tovalidate silicon electrical performance;

Qualification:

- MS with minimum of 3-5 years experiencein semiconductor industry, PhD preferred;

- Master’s Degree or PhD in a technicalfield;

- Minimum of 3-5 years experience in afield related to Semiconductor Device Modeling;

- Strong fundamental understanding ofsemiconductor process technology and analysis methodologies;

- Familiar with CMOS processes, RF devicecharacterization and IC design;

- Development of new active and passivedevices for RF CMOS technology;

- Fundamental understanding of SPICEModeling/CAD/EDA/PDK in general;

- Good data analysis, problem solving, andcommunication skills;

- Self-motivated, inventive, andresourceful;

The following traits are highly valued:

- Strong experience in simulation toolslike Spectre, HSPICE, ELDO, Ultrasim, ... and simulation methodologies;

- Familiar with Cadence Layout tools,Assura DRC/LVS;

- Familiar with DC/AC/RF devicecharacterization equipment (LCR meter, oscilloscope, vector network analyzers)and probe-station;

- Experience with TCAD process and devicesimulation tools;

- Proficient in scripting languagesMatlab/Python/Perl and experience with the Microsoft Office programs;

- Experience with EM Simulation tools(HFSS,...);

- Basic familiarity with UNIX/Linux;

- Strong organizational skills, to managemultiple tasks simultaneously and know how to set priorities according torequirements;

- Excellent verbal and writtencommunication skills;

- Ability to manage complete projects withvery limited supervision.

JOB TITLE: IC Design Engineer（display）

职位：IC设计工程师

JOB DESCRIPTION:

- Module-level architecture definition anddesign；

- Module-level RTL implementation；

- Simulation/Verification at both modulelevel and system level；

- Module-level synthesis and timinganalysis；

- Writing design spec and report；

- FPGA/silicon debug on related modules.

QUALIFICATION:

- MSEE with Minimum 2-year experience ondigital IC design

- Solid knowledge on digital IC design

- Strong skills of Verilog RTL coding andsimulation

- Hands-on experiences on EDA tools, suchas Cadence and Synopsys tools

- Familiar with C language

- Relevant experiences on video display areplus

- Hardworking and self-motivated

- A team player

JOB TITLE: IC Design Engineer（Analog)

职位：IC设计工程师（模拟）

JOB DESCRIPTION:

- Design, evaluate and verify high speedCMOS analog circuits.

- Oversee layout and verificationactivities which include floor plan, LVS and DRC.

- Generate design spec and write designreview document

- Engineering lab testing and chip debug

QUALIFICATION:

- MSEE,5 years or above working experiencein analog circuit design.

- Good fundamental in device physics,analysis and design of analog / mixed-signal circuits.

- Experience in Verilog, AHDL and/orMatlab.

- Ability to do layout floor plan andprovide verification/debugging guidance.

- Solid knowledge of EDA design tools.(Analog artist, spectre, HSPICE and nc-verilog ...)

- Design experience in any of the followingareas is preferred: PLL,  high-speedI/O’s, transceiver, LV-LP analog design

Key information:

IO、high speed、signal intergrity、PLL、low power、DDR、Memory、Flash-

JOB TITLE: IC Design Engineer（Digital)

职位：IC设计工程师（数字）

JOB DESCRIPTION:

- Micro-architecture definition/writing ICdesign spec；

- RTL coding for logic modules；

- Simulation/Verification offunctionalities at both module level and top level；

- Do module level synthesis / timinganalysis；

- Writing complete design/verificationreports；

- Silicon debug of the related modulefunctionalities；

- Writing test patterns for productiontests.

QUALIFICATION:

- MSEE with minimum 2-year experience ofdigital design experience;

- Experience on SERDES is preferred;

- Relevant experience in high-speed and lowpower digital design (Semi-flow: customer layout + ASIC flow) is must;

- Relevant experience in Cadence ICMS/ICFBdesign environment is must;

- Solid knowledge of digital designbuilding blocks (eg. Data-path, Synchronizer, FIFO...);

- Strong skills of Verilog RTL coding andverification and debug;

- Hands on experience in EDA tools such asCadence NC-Sim, Synopsys DC, PT, etc;

- Relevant experience in DDR interfacedesign is a plus;

- Self-motivated and team player.

Keyinformation:

DDR

JOB TITLE:  Senior IC Design Engineer（Digital)

职位：高级IC设计工程师（数字）

Job description:

- Micro-architecture definition/writing ICdesign spec.

- Model level behavior model built up andRTL coding

- Synchronization and asynchronous digitalcircuit design

- Simulation/verification offunctionalities at both module level and top level

- Script based synthesis & timinganalysis on GHz working frequency

- Design/verification report & reviewmeeting holding

- Silicon debug of related modelfunctionalities

- Sampler chip testing

Qualification:

- BSEE with minimum 8-year or MSEE withminimum 5-year experience of digital experience

- Relevant experience in high-speed digitaldesign (Semi-flow: customer layout + ASIC flow) is must

- Solid knowledge of high-speedasynchronous circuit design, family with standard cell architecture andbehavior

- Solid knowledge of mixed signal design,digital and analog interface

- Family with low-power-design flow

- Strong skills of Verilog RTL coding,verification and debug

- Hands on experience in EDA tools such asCadence NC-Sim, Synopsys DC, PT, etc.

- Solid knowledge of documentation ofdesign report

- Relevant experience on telecom timingchip is a plus

- Self-motivated and team player

Key information:

Digital-pll、high speed、asynchronous digitaldesign、DAC、ADC、Sigma-Deita

JOB TITLE: HarwareEngineer(WIFI)

职位：硬件应用工程师(WIFI)

工作地点：杭州

岗位职责：

1.Wi-Fi产品相关电路设计。

2. 硬件讯号量测，验证与除错。

3. 客户端Design In应用问题解决，提供客户技术支持，包含Schematicand PCB Layout review.

职位要求：

1.熟悉OrCAD 和Allegro or PADS ；

2. 5年以上工作经验，具有Wi-Fi相关产品经验。

3.电子，电机相关科系。

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

Mob:            18502155252

E-Mail:         Jane-Jin@hi-talent.com

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