Cadence招聘资深前端验证/设计工程师

kengteng

Cadence招聘资深前端验证/设计工程师

Title: Principal/Lead Verification Engineer (数字前端验证)
Location： SH/BJ
更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘
If you have interest, PLS send your update CV to zhangyl@cadence.com

  
Position Description:
Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:

-- Deep understanding on ASIC/SOC design flow
-- Excellent knowledge of advanced verification methodology like eRM/OVM/UVM
-- Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
--Proficiency in System Verilog,  System C and/or e (Specman)
-- Developing and using Verification Components (eVC, OVC, UVC, VIP)
-- Developing and using assertion based verification and formal analysis methods
--Skilled in scripting language, such as Perl, C shell, Makefile
-- Assessing the project verification requirements
-- Operating in a lead role regarding architecting and implementation of project   
     verification environment/solution.
-- May coordinate/lead others within the scope of a defined project

Position Requirements:
-- Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
-- Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.


Desirable Qualifications:
-- A minimum of seven years relevant experience in industry.
-- Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
-- Will have demonstrated successful completion of 10+ verification projects as an individual contributor
-Prefer to have DDR IP verification experience


Title: Principal Lead Design Engineer (数字前端设计)
Location: SH/BJ
更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow

- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design

* At least five years experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
  
Position Requirements:
1. Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written. 3. Requires good communication skills in English.