有关APB的一个菜鸟问题

大帅哥1989

在看APB的手册时有以下一句话：
It is recommended that the address and write signals are not changed immediately after a transfer but remain stable until another access occurs.

让我疑惑的是为什么只建议address 和 write 两个信号，而不包含data信号呢？
按说在下次传输之前data也没用啊，完全可以不管它。

问题2：
PREADY can take any value when PENABLE is LOW. This ensures that peripherals that have a fixed two cycle access can tie PREADY HIGH.
这什么意思？完全不懂。尤其是：peripherals that have a fixed two cycle access

小弟在这里多谢了~~~

barrent

顶起，让大神看到

大帅哥1989

再问一个，AXI spec上还有一句话也让我看醉了：
An interconnect between devices is equivalent to another device with symmetrical master and slave ports to which real master and slave devices can be connected.
是什么意思

大帅哥1989

register slice怎么解释？