回复 3# joemool
版主大大好可爱!哈哈。。刚get到的。略说下。
还有其中有一个setCTSMode -traceHonorConstants true|false 这个mode的设置会导致工具在trace clock的过程中,对SDC和netlist中的约束和常数解读不一样。 Honors the following SDC constraints capturedin the memory after reading the timing constraints file, and propagates theconstants when tracing the clock tree. * set_case_analysis * set_disable_timing * set_logic_one * set_logic_zero * 1'b0 and 1'b1 in the netlist When set to false, the software ignores theconstraints when tracing the clock tree. For example, it traces through an ANDgate, where the non-clock input pin has a set_case_analysis 0. When set totrue, the software stops propagating constants at the AND gate, and marks theclock input pin as an excluded pin. Default: false |