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本帖最后由 crystal_duan 于 2015-1-31 12:07 编辑
module xx(select,a,b,c,o);
input [1:0]select;
input [4:0] a,b,c;
output [4:0]o;
reg [4:0]o;
always@(a or b or c or select)
begin
case(select)
1=a;
2=b;
3=c;
default:o=a;
endcase
end
always_comb
begin
assert_select: assert ((select == 1)&&(o==a));
end
endmodule
module testbench;
reg [1:0]select;
reg [4:0]a,b,c;
wire [4:0] o;
reg clk,rst_n;
integer i;
initial begin
a=4;b=5;c=6;
rst_n = 0;
clk = 0;
#2;
rst_n= 1;
#3;
clk = 1;
for(i=0;i<100;i=i+1)
#5 clk = ~clk;
$stop;
end
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
select <=0;
else
select <= select+1;
end
xx xx_u(select,a,b,c,o);
bind xx xx_asser_chk chk_u(clk,select,a,b,c,o);
endmodule
module xx_asser_chk(clk,select,a,b,c,o);
input clk;
input [1:0]select;
input [4:0] a,b,c;
input [4:0]o;
property chk_sel;
@(posedge clk)(select == ($past(select) + 1));
endproperty
assert_sel: assert property (chk_sel);
cover_sel: cover property (chk_sel);
endmodule
在modelsim中运行:
vlog -sv -cover bset +acc=a xx.sv
vsim -assertcover -coverage testbench
run 60ns
运行结果:fail_count、pass_count、active count全部为0,为什么呀? |
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