Cadence SH 招聘Principal/Lead Customer Support Engineer -DDR PHY

kengteng

Cadence SH 招聘Principal/Lead Customer Support Engineer -DDR PHY

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com

Title: Principal/LeadCustomer Support Engineer -DDR PHY

  

Position Description:

Cadence is looking for an individual to work in anestablished DDR Design IP team. The group provides configurable DDR memorycontroller and PHY IP for ASICs. The job will be focused on providing technicalsupport to customers, however there will be a variety of other engineeringtasks that will allow the candidate to expand skills and responsibilities.

Provide technical support to customers for integration of IPinto ASICs including:

- Debugging of customers’ simulation or silicon issues

- Reviewing of customers’ integration of our IP

- Reviewing static timing reports to assist with customers’timing closure

- Answering technical questions about IP operation

- Train field engineers in IP operation

- Interface with the R&D and marketing teams to makeproduct improvements and resolve customer issues

PositionRequirements:

Essential Skills and experiences needed:

- Excellent oral and written communication skills in Chineseand English

- All front-end skills – RTL design & verification inVerilog, synthesis, static-timing analysis, DFT

- Time management skills sufficient to balance multiplehigh-priority projects

- Willingness to learn new skills and perform tasks thatoften go outside area of current expertise

Additional Desirable Qualifications:

- Back-end skills – place & route, physicalverification, timing closure, power analysis

- Experience with Static Timing scripts and report analysis

- Familiarity with DDR memory operation, system applications,AMBA protocols

- Scripting in Perl, TCL, etc.