【全职】NVIDIA招聘 ASIC Physical Design Engineer-SH

NVHR

Hi ALL，

本人NVIDIA HR Tracy，目前我们在上海招聘ASIC Physical Design Engineer的岗位，职位描述如下，大家有意向可以发送简历到tracyw@nvidia.com
我会尽快和大家联系：）

GPU ASIC Physical Design Engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic.

RESPONSIBILITIES:
Chip integration and netlist generation.
-Synthesis, Formal verification, netlist quality check.
Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level.
Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
Develop flow to physically partition and floorplan the entire chip.
Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:
BS or MS in Electrical Engineering or Computer Science
Years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
Excellent scripts skills
Excellent written and verbal communication skills in English
Ability to multiplex many issues, set priorities, and work in a team environment
Keep up to date with leading edge technologies

Best Regards
Tracy

QQ: 874416280

东方之子yj

好工作！