Asymmetric LDMOS 可以做传输门么？

istart_2002

   

Hi istart_2002:

How about the vds voltage, is it < 22V?

mpig
mpig09 发表于 2014-10-31 11:40

                               
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like switch K1,K2.
VDD is about 22.5V.CAP C1 will be charged to 1.25V.

MicroEpzc

   

mpig09 发表于 2014-10-30 22:54
Hi istart_2002:

You need to check VGS when the X=Y is meet device property or not.

Hi mpig09：
Here is a question I want to consult you that how to design the gate control circuit of this P-LDMOS switch when its source is connected to a cap and drain is connected to a PAD which its voltage varies  from zero to high voltage？Look forward to your reply!
Thank you！

MicroEpzc

前辈，请教一下，在一些stepwise对电容充放电的情况下， 会用p-LDMOS做开关，其source会接到电容，在建立过程中，source电压从0V逐渐升到平衡高压，那么他的栅极控制电路怎么去设计呢？既使他建立过程中能不断切换导通关断，也能不过压击穿栅氧，因为Vgs<5V