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[招聘] AMD上海研发中心招聘信息2则

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发表于 2014-10-30 14:38:32 | 显示全部楼层 |阅读模式

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AMD上海研发中心多岗位招聘火热进行中,请感兴趣的候选人务必以所应聘职位_姓名_学历_专业_现公司名称_工作年限
为标题,把简历以附件形式发送到maggie1.zhang@amd.com ,请在正文称述应聘理由与优势



GPUPerformance Verification and Analysis engineer

Title: Senior GPU Performance Verification andAnalysis engineer

>5 years’ experience with one of following:

a) Software: OGL/D3D driver background

b) 3D/GPU Architecture

l c) IC Design/verification Background

l d) CPU design/verification

l e) 3D Application programming etc.

f) Compiler Back Ground

g) Graphics Architecture

h) GPGPU related jobs

Description of duties in addition to those in jobdescription:

- Co-Work with World Wide Performance Verificationand Analysis Team

- Plan and Execute Performance Verification andAnalysis for new Project

- Continuous Team Growth

- Initiate and Lead Research on GPU architect

- Initiate Advanced Performance/Power Algorithms

- Write test plan for new graphics chips

- Write performance tests for new graphics chips

- Debug/Analysis performance bugs of graphics chips

- Debug function bugs for performance tests

- Write performance analysis tools for new graphicschips

- Function verification for new features of graphicschips

- Write benchmarks for new graphics chips

- GPGPU performance verification

Preferred Experience:

- Master Degree or Above

- 5 Years+ experience on people management

- 5 + year experience on C\C++

- Plus with experience on CPU/GPU Design/Verificaiton

- Plus with experience on Compiler

- Plus with 5+ years’ OpenGL/D3D programmingexperience

- Plus with 5+ years’ OpenGL/D3D driver experience

- Plus with 3+ years’ Linux/Shell

- Plus with 3+ years’ perl/python

- Familiar with Graphics Algorithm/Graphics Pipeline

- Proficient in English read/write/speaking/listening

- Good communication & Team worker

2.
MTS/SMTSASIC verification engineer-memory control

- Understand the architecture of the chip andfunctional block being designed

- Build C/C++ model for simulation

- Build test bench and monitors for DUT

- Compose test plan and validation vectors to ensurefunctional completeness

- Debug function/performance bugs of graphics chips

Preferred Experience:

- Major in EE, CS or related, Master Degree with 5+years or Bachelor with 7+ years working experiences

- Familiar with Linux Environment (including shellscripting and linux gnu tools)

- Experience with design for verification (assertionbased design strategies, code coverage, functional coverage, test plan,gate-level simulation, back-annotation etc.)

- Should be versatile in any one of the high levelverification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industrystandard tools for verification

- Should have excellent communication skills (bothwritten and oral)

- Strong problem solving skills

发表于 2014-10-30 16:09:14 | 显示全部楼层
不是全球裁员7%吗?怎么还招人?
发表于 2014-10-31 08:38:28 | 显示全部楼层
裁掉贵的,新招便宜的!
发表于 2014-11-4 12:24:09 | 显示全部楼层
内容为什么没有新人呢?新人应该更便宜啊
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