CMOS PLL Synthesizers Analysis and Design Keliu shu

jjp11951 · 发表于 2014-10-27 18:37:04

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Shu, Keliu; Sanchez-Sinencio, Edgar;

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This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly. This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers.

dcircuit · 发表于 2014-10-27 22:00:15

下来看看

acjeff · 发表于 2014-10-28 07:34:13

楼主辛苦了！正希望研究一下呢

apteye · 发表于 2014-10-28 08:58:51

wennuan

markhorrow · 发表于 2014-10-28 15:37:04

非常感谢提供！

AcoAco · 发表于 2014-10-29 16:12:10

这是发表在2004年或者是一个新的版本？

miaoya · 发表于 2014-11-1 06:39:21

回复 1# jjp11951
很好，要是有pdf版就更好了

rhk451 · 发表于 2014-11-3 10:25:33

goooooooooooooooooooood

wangjin0215 · 发表于 2014-11-7 00:52:15

看看，谢谢。。。。

kharthik · 发表于 2014-11-7 18:34:15

which version english or chines.?

CMOS PLL Synthesizers Analysis and Design Keliu shu

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