CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED A/D CONVERTERS

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好像是本好书，还是先等等大家的评议再下！

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters (The International Series in Engineering and Computer Science) (Hardcover)
by Robert A. I. Conant, Mikko E. Waltari, Kari A. I. Halonen

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Product Details

Hardcover: 265 pages
Publisher: Springer; 1 edition (May 5, 2005)
Language: English
ISBN: 1402072449

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Editorial Reviews

Book Description
The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field.

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http://www.amazon.com/Techniques ... ie=UTF8&s=books

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Editorial Reviews
Book Description
The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field.

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评价很好！

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Helsinki University of Technology, Electronic Circuit Design Laboratory
Report 33, Espoo 2002

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Keywords: analog integrated circuit, analog-to-digital conversion, BiCMOS, bootstrapped
switch, CMOS, double-sampling, IF-sampling, low voltage, operational amplifier,
pipelined analog-to-digital converter, sample-and-hold circuit, switched-capacitor,
switched-opamp, time interleaving.

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Preface
The greater becomes the volume of our sphere of knowledge, the greater
also becomes its surface of contact with the unknown.
Jules Sagret
The above quote was printed in a yellow postcard—an invitation message from the
student union—attached to the letter announcing my acceptance to the university in
1992. These ten years have really revealed me the wisdom of those words.
The research reported in this thesis has been carried out at Helsinki University of
Technology, Electronic Circuit Design Laboratory between 1997 and 2002. During
that time I have had a privilege of participating the Graduate School in Electronics,
Telecommunications, and Automation (GETA) and working with research projects
funded by Finnish National Technology Agency (TEKES) and Academy of Finland.
I want to express my gratitude to my supervisor professor Kari Halonen, who has
given me the opportunity of working with these interesting projects. The fruits of this
work wouldn’t have been what they are without him pushing the design goals higher
and encouraging to write and submit manuscripts to the topmost academic forums in
this field.
I am specially thankful for Lauri Sumanen, who has been my partner in the twoman
core team of Nyquist rate ADC research. His commitment and technical contribution
to the projects we have carried out together has been invaluable. The greatest
results of our cooperation are those two prototypes that we managed to publish in
Journal of Solid-State Circuits and International Solid-State Circuits Conference. The
junior team members in these projects, Jussi Pirkkalaniemi and Tuomas Korhonen,
also deserve a mention.
My warmest thanks also go to Marko “Pikkis” Kosunen, with whom I shared an
office for six years. Our daily discussions about technical and nontechnical matters is
one of the things I will miss most from the laboratory.
From among my senior colleagues, some of which have already left the laboratory,
I want specially mention Saska Lindfors, Jouko Vankka, and Kimmo Koli. Their help
in figuring out the strengths and weaknesses of my new ideas as well as finding the
relevant literature references has been irreplaceable. In addition to Pikkis and Saska
two other old-timers, Mika “Läkä” Länsirinne and Rami Ahola, have also been great
company to work and to have fun with.
Thanks for the exceptional atmosphere and team spirit in the laboratory belongs
to all these people as well as those not mentioned by name. However, two persons
whose impact has been especially strong are our secretary Helena Yllö and professor
Veikko Porra.
The reviewers of this thesis, professors S. H. Lewis and R. J. van de Plassche,
deserve my warmest thanks for their thorough acquaintance with the manuscript and
their valuable comments and suggestions.
Last but not least I must thank the home front. The support from my wife Miia
and her appreciation toward my work are those things that have helped me pushing on
when the amount of work yet to be done has seemed unbearable. I also want to thank
my parents Ritva and Eljas for the inspiring atmosphere in my childhood home, which
awoke my interest in sciences and led my way to the university.
Finally I want to acknowledge the financial support from the following foundations:
Nokia Oyj:n säätiö, Emil Aaltosen säätiö, Jenny ja AnttiWihurin rahasto, Tekniikan
edistämissäätiö, Elektroniikkainsinöörien säätiö, and HPY:n tutkimussäätiö.
Espoo, May 2002.
Mikko Waltari