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Please sent resume to hbaifenbai@126.com if you are intested in this position
1. Position Title:GPU ASIC Physical Design engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic RESPONSIBILITIES:
 Chip integration and netlist generation
 Synthesis, Formal verification, netlist quality check
 Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
 Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
 Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
 Develop flow to physically partition and floorplan the entire chip.
 Develop scripts for performing ECO's.
MINIMUM REQUIREMENTS:
 BS or MS in Electrical Engineering or Computer Science
 Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
2 | P a g e
 - Excellent scripts skills
 - Excellent written and verbal communication skills in English
 - Ability to multiplex many issues, set priorities, and work in a team environment
 - Keep up to date with leading edge technologies
Please sent resume to hbaifenbai@126.com if you are intested in this position |
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发表于 2014-10-20 17:53:27
