北京混合信号集成电路设计公司招聘: 数字集成电路设计与验证工程师 工作地点:上地

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IC Design & Verification Engineer (Junior/Intermediate/Senior &Manager): 数字集成电路设计与验证工程师
Position Summary:
? Top-level digital architecture planning including partition and interface to register maps.
? State machine, PHY (SPI, I2C, CAN), EEPROM, RAM, and ROM design.
? Verilog HDL based digital design: verification, synthesis, simulation and static timing analysis.
? Design for test including scan insertion, test pattern generation, and fault grading.
? Overseeing automatic cell place and route.
? Evaluation of silicon, test correlation, and scripting (Perl, Python, C++)
? Assisting support of customer applications.

Requirements:
? BSEE/MSEE/PhD with digital design experience
? Previous mixed signal product development experience including behavioral models of analog circuits and mixed mode simulation.
? Ability to work with both synthesized and hand generated digital designs.
? Experience with design prototyping and validation using FPGAs
? Familiarity with circuit layout including standard cell generation.
? Ability to work independently.
? Good writing and communication skills.

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