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Cadence SH 招聘Principal/Lead IP design Engineer 更多职位信息敬请关注Cadence公众微信平台:Cadence中国招聘
If you have interest, PLS send your update CV to zhangyl@cadence.com Title:Principal/Lead IP design Engineer Position Description: 1.Perform physical design implementation,including synthesis, floor planning, power grid design, place and route, clocktree synthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical designproject management. 2.The candidate will have the opportunity towork on many varieties of challenging designs, i.e. low power and high speeddesign. The responsibility includes participating in or leading next generationphysical design, methodology and flow development.
PositionRequirements: 1.BSdegree with 6~10+ years of applicable experience, MS degree with 4~7+ years ofapplicable experience in electrical engineering, microelectronics. 2. Experiencedwith ASIC design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues. Solid knowledgeon LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis,formal verification, physical verification, DFM. 3.Successful track records of taping outcomplex, 65/40/28 nm SOC chips. 4.Automationand programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl. 5.Self-motivated,able to work independently or as a team player 6.Excellentverbal and written communication skills in English. |