system level ESD protection-2014-springer

andyjackcao

2014 ESD 巨著
maxim  ESD 大牛 Vladislav A. Vashchenko 和Mirko Scholz 撰写
contents:
1 System Level ESD Design............................... 1
1.1 Understanding of ESD Events . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 IC and System-Level ESD Stress . . . . . . . . . . . . . . . . . 1
1.1.2 Trends in the IC Component and System
ESD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 On-Chip ESD Protection Strategies . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Rail-Based ESD Protection Network . . . . . . . . . . . . . . . 9
1.2.2 Local Clamp Network and Two Stage Protection . . . . . . 11
1.2.3 Multiple Voltage Domains . . . . . . . . . . . . . . . . . . . . . . 20
1.3 Off-Chip ESD Protection Strategies . . . . . . . . . . . . . . . . . . . . . 20
1.3.1 Trend Toward High Level Integration: SoC and SiP . . . . 21
1.3.2 ESD Voltage Suppression . . . . . . . . . . . . . . . . . . . . . . 22
1.3.3 Capacitance and Signal Integrity. . . . . . . . . . . . . . . . . . 26
1.3.4 ESD Suppressor Considerations
for Off-Chip Network . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4 Network Simulation with ESD Compact Models . . . . . . . . . . . . 34
1.4.1 ESD Compact Model for LV Devices . . . . . . . . . . . . . . 35
1.4.2 ESD Compact Model for HV Devices . . . . . . . . . . . . . . 36
1.5 On-Chip ESD Design with Mixed-Mode Circuit Simulation . . . . 40
1.5.1 Industrial ESD Development Workflow with TCAD . . . . 40
1.5.2 New Approach with Parameterized
Device and Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2 System Level Test Methods ............................. 51
2.1 Board Level Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . 52
2.1.1 General Electrical Equipment IEC 61000-4-2
Standard and Test Methodology . . . . . . . . . . . . . . . . . . 52
2.1.2 Automotive Standard ISO 10605. . . . . . . . . . . . . . . . . . 61
2.1.3 The Surge Standard IEC 61000-4-5. . . . . . . . . . . . . . . . 65
2.2 HMM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.2.1 HMM Setups with ESD Gun . . . . . . . . . . . . . . . . . . . . 73
2.2.2 50 Ohm HMM Setup. . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3 Transmission Line Pulsed Characterization . . . . . . . . . . . . . . . . 76
2.3.1 TLP Test Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.2 Very Fast TLP Test Method. . . . . . . . . . . . . . . . . . . . . 82
2.4 Transient Waveforms Characterization for ESD Stress . . . . . . . . 85
2.4.1 Calibration of ESD Waveforms . . . . . . . . . . . . . . . . . . 86
2.4.2 Transient Characterization of HV Circuits . . . . . . . . . . . 92
2.4.3 Transient Characterization with On-Wafer
HMM Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.5 HMM Tester Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.5.1 Test Setup and Device Characterization. . . . . . . . . . . . . 97
2.5.2 Impedance Matching and Impact on Failure Level . . . . . 104
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3 On-Chip System Level ESD Devices and Clamps ............. 111
3.1 Important Introductory Material for On-Chip ESD Design . . . . . 111
3.1.1 Local Clamp and Rail-Based Protection Network . . . . . . 111
3.1.2 Conductivity Modulation in Semiconductor Structures. . . 114
3.1.3 ESD Related Specifics in Integrated
Process Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.1.4 SOA in ESD Pulse Domain and Self-Protection . . . . . . . 126
3.2 Low Voltage ESD Devices for System-Level Protection . . . . . . 128
3.2.1 Non-snapback Solutions. . . . . . . . . . . . . . . . . . . . . . . . 129
3.2.2 SCR and LVTSCR Devices . . . . . . . . . . . . . . . . . . . . . 131
3.2.3 High Holding Voltage SCRs . . . . . . . . . . . . . . . . . . . . 137
3.2.4 Low Voltage Dual-Direction Devices . . . . . . . . . . . . . . 139
3.3 High-Voltage ESD Devices for System-Level Protection . . . . . . 143
3.3.1 High Voltage Active Clamps . . . . . . . . . . . . . . . . . . . . 144
3.3.2 LDMOS-SCR Devices . . . . . . . . . . . . . . . . . . . . . . . . . 146
3.3.3 High Holding Voltage HV Devices:
Avalanche Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
3.3.4 Lateral PNP ESD Devices . . . . . . . . . . . . . . . . . . . . . . 159
3.3.5 HV Dual Direction Devices . . . . . . . . . . . . . . . . . . . . . 161
3.4 ESD Cell Design Principles . . . . . . . . . . . . . . . . . . . . . . . . . . 165
3.4.1 Undesirable Multifinger Turn-On Effect . . . . . . . . . . . . 165
3.4.2 Poly Ballasting to Overcome Multi Finger
Turn-On Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
3.4.3 Overcoming Multi Finger Turn-On by Proper
Cell Layout Engineering . . . . . . . . . . . . . . . . . . . . . . . 174
3.4.4 Metallization Limitations and Optimization . . . . . . . . . . 176
3.5 Process Capability Index for ESD Devices . . . . . . . . . . . . . . . . 180
3.5.1 Understanding Process Capability Index
for ESD Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
3.5.2 Cpk Simulation for the Avalanche
Diodes Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.5.3 Cpk Analysis for the NLDMOS-SCR Clamp . . . . . . . . . 191
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
4 Latch-up at System-Level Stress .......................... 199
4.1 Conventional I/O and Core Latch-up . . . . . . . . . . . . . . . . . . . . 200
4.1.1 Latch-up Simulation Structures . . . . . . . . . . . . . . . . . . . 200
4.2 High Voltage Latch-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
4.2.1 Nepi-Nepi Latch-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.2.2 Active Guard Ring Isolation and Experimental
Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
4.2.3 HV Latch-up Prevention Rules . . . . . . . . . . . . . . . . . . . 222
4.3 Transient Induced Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . 223
4.3.1 Test Approach for TLU . . . . . . . . . . . . . . . . . . . . . . . . 224
4.3.2 TLU in Case of Switch Pins in Power Trains . . . . . . . . . 224
4.3.3 TLU, Simple Network with Standalone ESD Devices . . . 228
4.3.4 TLU. Impact of the On- and Off-chip
Protection Networks . . . . . . . . . . . . . . . . . . . . . . . . . . 230
4.4 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
4.4.1 LIN and CAN Transceivers . . . . . . . . . . . . . . . . . . . . . 236
4.4.2 CAN Transceiver Case Study . . . . . . . . . . . . . . . . . . . . 240
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
5 IC and System ESD Co-design ........................... 247
5.1 Off-Chip ESD Protection with Si TVS Components . . . . . . . . . 248
5.1.1 Silicon TVS Device Structure. . . . . . . . . . . . . . . . . . . . 248
5.1.2 Silicon TVS Characteristics . . . . . . . . . . . . . . . . . . . . . 252
5.2 System-Level ESD Design Modeling and Simulation. . . . . . . . . 252
5.2.1 ESD Tester Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
5.2.2 Representation of ESD Devices
with Behavioral Models . . . . . . . . . . . . . . . . . . . . . . . . 254
5.2.3 TVS Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
5.2.4 Modeling of Board-Level Passive Components . . . . . . . . 258
5.2.5 Mixed-Mode Simulation . . . . . . . . . . . . . . . . . . . . . . . 260
5.3 Datasheet-Based System Level ESD Design . . . . . . . . . . . . . . . 261
5.4 IC-System ESD Co-design Concept . . . . . . . . . . . . . . . . . . . . . 265
5.4.1 The Co-design Methodology with TLP Data . . . . . . . . . 266
5.4.2 IC-System Co-design with Additional HMM Testing . . . 268
5.4.3 Co-design Flow with TLP and HMM Testing. . . . . . . . . 275
5.5 System-Aware On-Chip ESD Protection Design . . . . . . . . . . . . 276
5.5.1 Experimental Setup for the Case Study . . . . . . . . . . . . . 276
5.5.2 Selection of ESD Clamps for External IC Pins . . . . . . . . 277
5.5.3 Co-design in Advanced CMOS Technologies . . . . . . . . . 284
5.5.4 Guidelines for Component-Level ESD Design . . . . . . . . 286
5.6 Comparison of System-Level ESD Co-design Methodologies . . . 292
5.6.1 Design with Datasheet Information . . . . . . . . . . . . . . . . 293
5.6.2 Design with Additional TLP Characterization. . . . . . . . . 300
5.6.3 Design Optimization with HMM Testing . . . . . . . . . . . . 303
5.6.4 Benchmarking and Comparison of the Designs . . . . . . . . 303
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
5.8 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
References ............................................ 311
Index ................................................ 319

louisl

E文 吃不消

fmyanglee

nice
wow
cool

ituluck

very good..

facteur

非常酷，真的，虽然我也不看。。。

student321

下来看看

zhujihan

非常新的书呀。E文T_T
有中文的书籍推荐吗

crazyboy

下载下来看看，辛苦LZ！！

vincent_long

谢谢分享

andy2000a

system level ESD 應該 和 surge 類都有關