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楼主: 真我个性

RHEL6.x86_64位系统Cadence ic616和Mmsim13安装教程

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发表于 2016-4-8 14:12:56 | 显示全部楼层
看看教程,自己安装一直提示错误
发表于 2016-4-11 21:12:31 | 显示全部楼层
按照论坛上,一步一步来,最后还是出问题了,搞不懂。求大神帮忙看看。
---
13:40:12 (lmgrd)   Please Note:
13:40:12 (lmgrd)
13:40:12 (lmgrd)   This log is intended for debug purposes only.
13:40:12 (lmgrd)   In order to capture accurate license
13:40:12 (lmgrd)   usage data into an organized repository,
13:40:12 (lmgrd)   please enable report logging. Use Flexera Software, Inc.'s
13:40:12 (lmgrd)   software license administration  solution,
13:40:12 (lmgrd)   FLEXnet Manager, to  readily gain visibility
13:40:12 (lmgrd)   into license usage data and to create
13:40:12 (lmgrd)   insightful reports on critical information like
13:40:12 (lmgrd)   license availability and usage. FLEXnet Manager
13:40:12 (lmgrd)   can be fully automated to run these reports on
13:40:12 (lmgrd)   schedule and can be used to track license
13:40:12 (lmgrd)   servers and usage across a heterogeneous
13:40:12 (lmgrd)   network of servers including Windows NT, Linux
13:40:12 (lmgrd)   and UNIX. Contact Flexera Software, Inc. at
13:40:12 (lmgrd)   www.flexerasoftware.com for more details on how to
13:40:12 (lmgrd)   obtain an evaluation copy of FLEXnet Manager
13:40:12 (lmgrd)   for your enterprise.
13:40:12 (lmgrd)
13:40:12 (lmgrd) -----------------------------------------------
13:40:12 (lmgrd)
13:40:12 (lmgrd)
13:40:12 (lmgrd) FLEXnet Licensing (v11.10.0.3 build 96543 i86_lsb) started on ivan (linux) (4/11/2016)
13:40:12 (lmgrd) Copyright (c) 1988-2011 Flexera Software, Inc. All Rights Reserved.
13:40:12 (lmgrd) US Patents 5,390,297 and 5,671,412.
13:40:12 (lmgrd) World Wide Web:  http://www.flexerasoftware.com
13:40:12 (lmgrd) License file(s): /home/ivan/cadence/ic616/share/license/license.dat
13:40:12 (lmgrd) lmgrd tcp-port 5280
13:40:12 (lmgrd) Starting vendor daemons ...
13:40:12 (lmgrd) Started cdslmd (internet tcp_port 46874 pid 3693)
13:40:12 (cdslmd) FLEXnet Licensing version v11.10.0.3 build 96543 i86_lsb
13:40:12 (cdslmd) Server started on ivan for: 111  
13:40:12 (cdslmd) 12141  206  21060  
13:40:12 (cdslmd) 21400  276  32150  
13:40:12 (cdslmd) 32760  365  940  
13:40:12 (cdslmd) 945  ABVIP_AHB ABVIP_AXI
13:40:12 (cdslmd) ABVIP_DFI ABVIP_OCP ACC_VIP_ACE
13:40:12 (cdslmd) ACC_VIP_AHB ACC_VIP_APB ACC_VIP_AXI_3_4
13:40:12 (cdslmd) ACC_VIP_DBI ACC_VIP_ETHERNET_1G_10G ACC_VIP_ETHERNET_25G50G
13:40:12 (cdslmd) ACC_VIP_ETHERNET_40G_100G ACC_VIP_HDMI_14 ACC_VIP_I2C
13:40:12 (cdslmd) ACC_VIP_I2S ACC_VIP_KPD ACC_VIP_MPC
13:40:12 (cdslmd) ACC_VIP_MPDI ACC_VIP_PCIE_3 ACC_VIP_SATA_6G
13:40:12 (cdslmd) ACC_VIP_SCD ADE_GXL_TC_Cockpit ADE_GXL_TC_DCM
13:40:12 (cdslmd) ADE_GXL_TC_MTS ADE_GXL_TC_MismatchAnalysis ADE_GXL_TC_Optimizer
13:40:12 (cdslmd) ADE_GXL_TC_PAD ADE_GXL_TC_SensitivityAnalysis ADE_GXL_TC_Tuner
13:40:12 (cdslmd) ADE_GXL_TC_YieldAnalysis ADE_GXL_TC_YieldOptimizer Affirma_sim_analysis_env
13:40:12 (cdslmd) Allegro_Auth_HighSpeed_Option Allegro_FPGA_System_2FPGA Allegro_FPGA_System_Planner_L
13:40:12 (cdslmd) Allegro_PCB_HighSpeed_Option Allegro_PCB_Mini_Option Allegro_PCB_Router_610
13:40:12 (cdslmd) Allegro_performance Allegro_studio Allegro_studio_Router_610
13:40:12 (cdslmd) AllegroSigrity_Pkg_Extract_Opt AllegroSigrity_SI_Base AMS_Designer_Link
13:40:12 (cdslmd) AMS_Designer_Verification AMS_environment Analog_Design_Environment_GXL
13:40:12 (cdslmd) Analog_Design_Environment_L Analog_Design_Environment_XL Assertion_Based_VIP_AXI4_ACE
13:40:12 (cdslmd) Assura_DRC Assura_DV_design_rule_checker Assura_DV_LVS_checker
13:40:12 (cdslmd) Assura_DV_parasitic_extractor Assura_LVS Assura_MP
13:40:12 (cdslmd) Assura_UI Base_Verilog_Lib C_to_Silicon_Compiler_L
13:40:12 (cdslmd) Cadence_chip_assembly_router Cadence_Framework_Runtime Cadence_Software_Developer
13:40:12 (cdslmd) Cadence_System_Creator Cadence_System_Creator_Inter CMP_Process_Optimizer
13:40:12 (cdslmd) CMP_Predictor Conformal_Asic Conformal_Cnstrnt_Dsgnr_L_LL
13:40:12 (cdslmd) Conformal_Cnstrnt_Dsgnr_XL_LXL Conformal_Custom Conformal_ECO
13:40:12 (cdslmd) Conformal_ECO_GXL Conformal_Low_Power Conformal_Low_Power_GXL
13:40:12 (cdslmd) Conformal_Ultra desktop_manager DFM_Core_Technology
13:40:12 (cdslmd) Digital_Mixed_Signal_Option Distributed_Dracula_Option DRAC2CORE
13:40:12 (cdslmd) DRAC3CORE DRAC3DRC DRAC3LVS
13:40:12 (cdslmd) DRACDIST DRACERC  DRACLPE  
13:40:12 (cdslmd) DRACLVS  DRACPRE  EDI_System_Block_Design
13:40:12 (cdslmd) EDI_System_Hier_Design EDI_CPU_Accelerator_GXL Enc_Test_Adv_MBIST_option
13:40:12 (cdslmd) Enc_Test_LBIST_option Encounter_Adv_Node_GXL Encounter_C
13:40:12 (cdslmd) Encounter_ccopt_GXL Encounter_Clck_Cncrnt_Opt_GXL Encounter_DFM
13:40:12 (cdslmd) Encounter_DFM_GXL Encounter_Diagnostics_Volume Encounter_Digital_Impl_Sys_L
13:40:12 (cdslmd) Encounter_Digital_Impl_Sys_XL Encounter_GigaScale_GXL Encounter_Library_Char_XL
13:40:12 (cdslmd) Encounter_Low_Power_GXL Encounter_Mixed_Signal_GXL Encounter_Pow_Sys_Adv_Anls_GXL
13:40:12 (cdslmd) Encounter_Power_System_L Encounter_Power_System_XL Encounter_QRC_Extraction_GXL
13:40:12 (cdslmd) Encounter_QRC_Extraction_L Encounter_QRC_Extraction_XL Encounter_S20_GXL
13:40:12 (cdslmd) Encounter_Stack_Die_GXL Encounter_T20_GXL Encounter_Test_Architect
13:40:12 (cdslmd) Encounter_Test_ExtensionLang Encounter_Tim_Sys_Adv_Anls_GXL Encounter_Timing_System_L
13:40:12 (cdslmd) Encounter_Timing_System_XL Encounter_True_Time Encounter_U20_GXL
13:40:12 (cdslmd) Encounter_Wave_Viewer enterprise_manager ET_Hierarchical_Option
13:40:12 (cdslmd) expgen  Extended_Verilog_Lib First_Encounter_L
13:40:12 (cdslmd) First_Encounter_XL Formal_Analysis_Option Functional_Safety_Simulator
13:40:12 (cdslmd) Incisive_Design_Team_Simulator Incisive_Desktop_Manager Incisive_Enterprise_ESL_Option
13:40:12 (cdslmd) Incisive_Enterprise_ESL_inter Incisive_Enterprise_Manager Incisive_Enterprise_Planner
13:40:12 (cdslmd) Incisive_Enterprise_Simulator Incisive_Enterprise_Verifier Incisive_Formal_Verifier
13:40:12 (cdslmd) Incisive_HDL_Simulator Incisive_P2C_Methodology Incisive_Specman_Elite
13:40:12 (cdslmd) Incisive_Specman_interactive Incisive_Verif_Environ LEAPFROG-CV
13:40:12 (cdslmd) Liberate_AMS_Client Liberate_AMS_Server Liberate_Client
13:40:12 (cdslmd) Liberate_LV_Client Liberate_LX_Client Liberate_LV_Server
13:40:12 (cdslmd) Liberate_LX_Server Liberate_MX_Client Liberate_MX_Server
13:40:12 (cdslmd) Liberate_Server Litho_DP_Client Litho_Electrical_Analyzer
13:40:12 (cdslmd) Litho_Physical_Analyzer MaskCompose_Definition MM_ddr3sdram
13:40:12 (cdslmd) MM_ddr4_lrdimm MM_ddr4sdram MM_emmc_45
13:40:12 (cdslmd) MM_emmc_50 MM_flash_onfi3 MM_flash_ppn_ddr
13:40:12 (cdslmd) MM_flash_toggle2_nand MM_hbm  MM_HMC  
13:40:12 (cdslmd) MM_lpddr3 MM_lpddr4 MM_lrdimm
13:40:12 (cdslmd) MM_PORTFOLIO_CATALOG MM_PORTFOLIO_PLUS_B MM_sdcard30
13:40:12 (cdslmd) MM_sdcard40 MM_UFS  MM_wideIO_2
13:40:12 (cdslmd) MM_wideIOsdram MTI_Opt_Incisive_Specman_Sim NanoRoute_Ultra
13:40:12 (cdslmd) OASIS_RFDE OASIS_Simulation_Interface PCB_design_studio
13:40:12 (cdslmd) PCB_librarian_expert pcomp  Performance_Option_To_Incisive
13:40:12 (cdslmd) Phys_Ver_Sys_ADP_Ex_Opt Phys_Ver_Sys_Adv_Ana_Opt Phys_Ver_Sys_Adv_Device
13:40:12 (cdslmd) Phys_Ver_Sys_Const_Validator Phys_Ver_Sys_Design_Ana Phys_Ver_Sys_DRC_XL
13:40:12 (cdslmd) Phys_Ver_Sys_Graph_LVS_Debug Phys_Ver_Sys_LVS_XL Phys_Ver_Sys_MRC
13:40:12 (cdslmd) Phys_Ver_Sys_Pattern_Match Phys_Ver_Sys_Prog_ERC Phys_Ver_Sys_Results_Mgr
13:40:12 (cdslmd) plotVersa PSpiceStudio PVS_MPT_Image_Decomposer
13:40:12 (cdslmd) PVS_MPT_Spacer_Decomposer QRC_Advanced_Analysis QRC_Advanced_Modeling
13:40:12 (cdslmd) QRC_Advanced_Modeling_20 QRC_Advanced_Node_Modeling QRCX_Display_Technology_Option
13:40:12 (cdslmd) QuickView_CH_SL QuickView_GDSII QuickView_GL1
13:40:12 (cdslmd) QuickView_HITACHI QuickView_JEOL QuickView_LAFF
13:40:12 (cdslmd) QuickView_MEBES QuickView_OA QuickView_OASIS
13:40:12 (cdslmd) QuickView_SemiP10 QuickView_Signoff QuickView_TOSHIBA
13:40:12 (cdslmd) RELXPERT RTL_Compiler_Adv_Phys_Option RTL_Compiler_CPU_Accel_Option
13:40:12 (cdslmd) RTL_Compiler_L RTL_Compiler_L_Option RTL_Compiler_Low_Power_Option
13:40:12 (cdslmd) RTL_Compiler_Physical RTL_Compiler_Ultra RTL_Compiler_Ultra_II_Option
13:40:12 (cdslmd) RTL_Compiler_Verification RouteMVIA_ALL Sim_Cov_UNR
13:40:12 (cdslmd) SiP_Layout_XL skillDev SMG_Create
13:40:12 (cdslmd) SMG_Runtime SOC_PORTFOLIO_CATALOG SPECCTRA_autoroute
13:40:12 (cdslmd) SPECCTRA_expert SPECCTRA_HP SPECCTRA_PCB
13:40:12 (cdslmd) SPECCTRAQuest SPECCTRAQuest_SI_expert SPECCTRAQuest_signal_expert
13:40:12 (cdslmd) Spectre_Burst_AllegroSI Spectre_char_opt Spectre_XPS
13:40:12 (cdslmd) TEMPUS_TIMING_SIGNOFF_L TEMPUS_TIMING_SIGNOFF_MP TEMPUS_TIMING_SIGNOFF_TSO
13:40:12 (cdslmd) TEMPUS_TIMING_SIGNOFF_XL Test_Design_Analysis Test_Design_Generation
13:40:12 (cdslmd) Test_Design_Verification Test_Extension_Language Test_Mfg_Analysis
13:40:12 (cdslmd) Test_Mfg_Fault_Isolation ULTRASIM_L Variety_LX_Client
13:40:12 (cdslmd) Variety_LX_Server Variety_MX_Client Variety_MX_Server
13:40:12 (cdslmd) VCS_Opt_Incisive_Specman_Sim VDS_Power VDS_Timing
13:40:12 (cdslmd) verifault VERILOG-XL VIP_802_11_MAC
13:40:12 (cdslmd) VIP_AHB_UVC VIP_AMBA5_CHI VIP_AXB_PS
13:40:12 (cdslmd) VIP_AXI_3_4 VIP_AXI_3_4_UVC VIP_AXI_PS
13:40:12 (cdslmd) VIP_AXI4_ACE VIP_AXI4_STREAM VIP_CAN  
13:40:12 (cdslmd) VIP_DISPLAYPORT VIP_ETHERNET_25G VIP_ETHERNET_40G_100G_PS
13:40:12 (cdslmd) VIP_ETHERNET_40G_100G_UVC VIP_ETHERNET_PS VIP_ETHERNET_TRIPLECHECK
13:40:12 (cdslmd) VIP_ETHERNET_UVC VIP_HDMI_14 VIP_HDMI_20
13:40:12 (cdslmd) VIP_I2C  VIP_INTERCONNECT_WORKBENCH VIP_JTAG
13:40:12 (cdslmd) VIP_LIN  VIP_MHL3 VIP_MIPI_CPHY
13:40:12 (cdslmd) VIP_MIPI_CSI VIP_MIPI_CSI_3 VIP_MIPI_DSI
13:40:12 (cdslmd) VIP_MIPI_LLI VIP_MIPI_MPHY VIP_MIPI_SLIMBUS
13:40:12 (cdslmd) VIP_MIPI_SOUNDWIRE VIP_MIPI_UNIPRO VIP_MR_IOV_PS
13:40:12 (cdslmd) VIP_NVME_PS VIP_OCP  VIP_OCP3
13:40:12 (cdslmd) VIP_PCI_UVC VIP_PCIE_1_2_PS VIP_PCIE_3_MPHY
13:40:12 (cdslmd) VIP_PCIE_3_PS VIP_PCIE_3_PURESUITE VIP_PCIE_3_TRIPLECHECK
13:40:12 (cdslmd) VIP_PCIE_4 VIP_PCIE_PURESUITE VIP_PLB  
13:40:12 (cdslmd) VIP_PLB_6 vip_portfolio VIP_PORTFOLIO_CATALOG
13:40:12 (cdslmd) VIP_PUREVIEW VIP_SAS  VIP_SAS_12G
13:40:12 (cdslmd) VIP_SATA_6G VIP_SATA_PS VIP_SR_IOV_PS
13:40:12 (cdslmd) VIP_SRIO VIP_SRIO3 VIP_SSIC
13:40:12 (cdslmd) VIP_UART VIP_UNIPRO_TRIPLECHECK VIP_USB_2_PS
13:40:12 (cdslmd) VIP_USB_3_PS VIP_USB_3_PURESUITE VIP_UVC_3PSI_ENGINE
13:40:12 (cdslmd) VIP_VALIDATOR_BASIC VIP_VALIDATOR_COHERENT Virtuoso_Acceler_Parallel_L
13:40:12 (cdslmd) Virtuoso_Acceler_Parallel_sc Virtuoso_Acceler_Parallel_XL Virtuoso_Adv_Node_Framework
13:40:12 (cdslmd) Virtuoso_Adv_Node_Opt_Layout Virtuoso_Adv_Node_Opt_Lay_Std Virtuoso_Constraint_API
13:40:12 (cdslmd) Virtuoso_Constraint_Interface Virtuoso_Core_Characterizer Virtuoso_Core_Optimizer
13:40:12 (cdslmd) Virtuoso_custom_placer Virtuoso_custom_router Virtuoso_DFM_option
13:40:12 (cdslmd) Virtuoso_Digital_Implem Virtuoso_Digital_Implement Virtuoso_Digital_Implem_XL
13:40:12 (cdslmd) Virtuoso_Digital_Implement_XL Virtuoso_Digital_Signoff_Power Virtuoso_DRC_Opt
13:40:12 (cdslmd) Virtuoso_EAD_3D_Prec_Solver Virtuoso_EAD_Adv_Elect_Analysi Virtuoso_IPVS_Adv_Ana_Opt
13:40:12 (cdslmd) Virtuoso_Layout_Migrate Virtuoso_Layout_Suite_EAD Virtuoso_Layout_Suite_GXL
13:40:12 (cdslmd) Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL Virtuoso_LDE_Analyzer
13:40:12 (cdslmd) Virtuoso_MixedSignalOpt_Layout Virtuoso_MMSIM_CPU_Accelerator Virtuoso_MMSIM_pwr_opt
13:40:12 (cdslmd) Virtuoso_MMSIM_RF_analysis Virtuoso_Multi_mode_Simulation Virtuoso_NeoCircuit_DFM
13:40:12 (cdslmd) Virtuoso_Oasis_API Virtuoso_Phase_Designer Virtuoso_Power_System_L
13:40:12 (cdslmd) Virtuoso_Power_System_L_EXT Virtuoso_Power_System_XL Virtuoso_QRC_Extraction_GXL
13:40:12 (cdslmd) Virtuoso_QRC_Extraction_L Virtuoso_QRC_Extraction_XL Virtuoso_Schematic_Editor_GXL
13:40:12 (cdslmd) Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL Virtuoso_Spectre
13:40:12 (cdslmd) Virtuoso_Spectre_GXL Virtuoso_Spectre_RF Virtuoso_Spectre_XL
13:40:12 (cdslmd) Virtuoso_Stack_Die_Option Virtuoso_Variation_Analysis_Op Virtuoso_Visual_Analysis_XL
13:40:12 (cdslmd) Virtuoso_Waveform_API VLS_GXL_TC_Analog_Auto_Placer VLS_GXL_TC_Cell_Planner
13:40:12 (cdslmd) VLS_GXL_TC_Cockpit VLS_GXL_TC_Digital_Auto_Placer VLS_GXL_TC_Floorplanning
13:40:12 (cdslmd) VLS_GXL_TC_Layout_CE VLS_GXL_TC_Layout_Migrate VLS_GXL_TC_Layout_Yield_Optimi
13:40:12 (cdslmd) VLS_GXL_TC_Module_Generator VLS_GXL_TC_Space_based_Router VLS_GXL_TC_VCAR
13:40:12 (cdslmd) VLS_GXL_TC_VLS_GXL VLS_GXL_TC_VPLGen vmanager
13:40:12 (cdslmd) vmanager_client vmanager_project Voltus_Power_Integrity_AA
13:40:12 (cdslmd) Voltus_Power_Integrity_AA_GXL Voltus_Power_Integrity_Fi_L Voltus_Power_Integrity_Fi_XL
13:40:12 (cdslmd) Voltus_Power_Integrity_L Voltus_Power_Integrity_MP Voltus_Power_Integrity_XL
13:40:12 (cdslmd)
13:40:12 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
13:40:12 (cdslmd)
13:40:12 (cdslmd) EXTERNAL FILTERS are OFF
13:40:12 (lmgrd) cdslmd
发表于 2016-4-17 00:45:49 | 显示全部楼层
谢谢分享!
发表于 2016-4-17 10:06:54 | 显示全部楼层
感谢分享,玩个cadence不容易呀,完全不懂linux的操作。。
发表于 2016-4-26 20:43:03 | 显示全部楼层
回复 1# 真我个性


   谢谢分享
发表于 2016-5-26 10:47:00 | 显示全部楼层
Thanks. the installation guide is very clear.
发表于 2016-7-9 16:21:09 | 显示全部楼层
看看,希望有用
发表于 2016-7-12 13:56:21 | 显示全部楼层
谢谢分享,可是我在电脑上装的时候总是无法跳出图形界面,在选disk的时候提示错误
发表于 2016-7-17 10:40:14 | 显示全部楼层
谢谢楼主了
发表于 2016-7-22 16:02:08 | 显示全部楼层
看看..........
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