Cadence SH 招聘高级数字后端产品测试工程师

kengteng

Cadence SH 招聘高级数字后端产品测试工程师

Job location: Shanghai

欢迎有工作经验人士和应届博士生投递

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you haveinterest, PLS send your update CV to zhangyl@cadence.com

1.   LeadProduct Validation Engineer-STA

Position Description:     

1. Cadence ICD Product Validation Analysis Teammainly focus on STA and Low Power related area in digital design backend flow.

2. This position is responsible for developing,applying and improving quality standard   

for Cadence Lower Power flow and Encountercommon timing engine .

3.The candidate needs to test Low PowerSolution and timing analysis result in

common and special usage flows.

Detailed Responsibility:

1.Identify Low Power solution and timingsign-off challenges in complex SOC designs and advacned process nodes

2.Proactively provide Low Power & STA &Sign-off development suggestions to R&D.

3.Build up Lower Power & STA & Sign-Offexpertise and deliver support to field team and customers whenever needed.

4.Required to acquire expertise and ownershipover existing product components as well as develop brand new product features.

5.Project leader on important Low Power or STAfeatures.

Position Requirements:

1.Bachelor with 6 years related experience orMaster with 4 years related experience in design house, FAB or EDA company.

2.Rich experience in IC design flow (front-endor back-end).

3.Experience in STA and SI analysis, orexperience in Low Power flow, knowledge in parasitic extraction and signoff isa strong plus.

4. Good Unix System knowledge and script skillof TCL/TK/CSH/PERL.

5.Excellent capability of self-learning,problem solving skills;

6.Being proactive and self-motivated;

7.strong leadership;

8.Good written English and oral English is astrong plus

2.   SeniorProduct Validation Engineer

Position Description:         

Work in Encounter NanoRoute Product Validation team. Theresponsibilities include:

1. Assistin Cadence EDI flow development and validation

2.Validate and maintain comprehensive NanoRoute unit and flow test cases forEncounter Digital Implementation System.

3.Develope test suites of the new features of Cadence's EDI router.

      Position Requirements:   

1.CS/EEBS degree with 3+ years or MS degree with 1+ year work experience

2.DigitalIC design knowledge is necessary, physical verification (DRC/LVS) and layoutknowledge is plus

3.UnixSystem knowledge, vi/TCL/TK/CSH/Perl will be plus.

4.Goodcommunication in English and Chinese, good confidence and self-motivation.

3. SeniorProduct Validation Engineer (for GPS)

PositionDescription:

This engineer will work in Encounter GPS(Global Physical Synthesis) product validation team. The responsibilitiesinclude:

a) Assist in Cadence EDI development andvalidation

b) Validate and maintain comprehensive GPS unitand flow test cases for Encounter Digital Implementation System.

c) Develop test suites of the new features ofEDI GPS function

PositionRequirements:

a)MS of EE/CS

b)Digital IC design knowledge is necessary,statistic timing analysis knowledge is a strong plus

c)Unix System knowledge, vi/TCL/TK/CSH/Perlwill be plus.

d)Good communication in English and Chinese,good confidence and self-motivation.