For a given design, typically there are at least two modes: afunctional mode and a test mode. Between those modes, conflicting clock pindefinitions may exist, as illustrated below.
In the functional mode, a generated clock is defined at pin Qof the clock divider, Div. This will result in a non-stop pin, Div/CLK, for thefunctional mode. However, in the test mode, a generated clock is not defined atDiv/Q. CTS tools will treat Div/CLK as a leaf pin or stop pin and try tobalance the path through Div with all of the other flops FFs1 and FFs2. This isneither possible nor something that designers want. Div is a clock divider andshould not be tested by scan, and hence, Div/CLK should be ignored.
The rightsequence of steps for a CTS tool is to first synthesize FCLK1 and FCLK2 in thefunctional mode. Next, in the test mode, set Div/CLK to be ignored andsynthesize SCLK.
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发表于 2014-7-21 19:23:40
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发表于 2014-12-11 12:47:05
