Synopsys武汉 IP Center 热招ASIC/ Verification Engineer for DDR USB

Domiliu

If you have any interest in the position, please send your bilingual resume as

attachments to
dmliu@synopsys.com

Subject of your email should be “Your Name_ University_ Applied Position Title_ Location”

1\ Job Title: Digital IP Designer ( ASIC Design or Verification_
USB DDR MIPI SATA)

Location: Wuhan

http://search.51job.com/job/53774338,c.html

Job responsibilities include understanding connectivity protocols like SATA, MIPI, SDMMC, AMBA, HDMI and working on the design/directed verification of designs in such protocols.

Be able to implement test benches and test cases in HDL like Verilog is needed.

Requirements:

- Has BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:

- Has good background in RTL design and directed verification. Hands on experience with Verilog coding and Simulation tools

-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog

-Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background

2\Job Title: Mixed-signal IP Designer (Digital Design or Verification for

SerDes/ DDR PHY)

Location: Wuhan

Job Responsibilities:

-
Develop and execute verification for IP level functional features related to DDR memory system.

-
Work closely with Design/Macro teams to identify the milestones and quality metrics of the project that includes scoping, tracking and delivery.

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Participate in test environment infra and regression infra development, testbench development in VMM/SystemVerilog/C++, test cases development and debug.

Requirements

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Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

-
Verification experience of IP core or ASIC Design for DDR memory system or mix-signal system.

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Hands on experience with creating test plan and test environment from Functional Specifications/ Test Environment Specifications with verification methodology of VMM/UVM.

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Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts.

袁斌

domi liu,你好，居然在这里碰见你了

Domiliu

回复 3# 袁斌


    哈哈 是啊 有合适的人欢迎推荐！

Domiliu

Global 著名 IC公司 武汉R&D center扩招中，机会不容错过！

axe001

为何非要有IC经验啊，做FPGA的应该可以考虑考虑啊。