NVIDIA英伟达上海急招ASIC Physical Design Engineer

NVHR

亲们，
NVIDIA上海最近急招多位asic Physical Design Engineer, 需要3年及以上工作经验的。以下是职位描述，有兴趣的童鞋可以将简历发至：sasu@nvidia.com 或者加QQ详聊：524786472

GPU ASIC Physical Design engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining thechip infrastructure process across product designs, focusing on full chiplayout planning (partitioning, planning clock distribution and other structure,methodology), partition/full chip timing closure (primetime scripts, othertools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

·        Chipintegration and netlist generation

·        -Synthesis,Formal verification, netlist quality check

·        Workin conjunction with Place and Route Engineers to achieve timing closure forboth partition level and full chip level

·        Developand enhance entire timing flow from frontend (pre-layout) to backend(post-layout) at both chip and block level.

·        Developcustom timing scripts using tcl/primetime for clock skew analysis, specialcircuits such as clock dividers, core logic <-> IO macros interfaces suchas PCI-E, Frame-Buffer/Memory, TMDS, etc.

·        Developflow to physically partition and floorplan the entire chip.

·         Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:

·        BSor MS in Electrical Engineering or Computer Science

·        Above3 years of relevant ASIC experience ideally with a focus in the chipintegration /synthesis/formal and timing closure

·        -Excellent scripts skills

·        -Excellent written and verbal communication skills in English

·        -Ability to multiplex many issues, set priorities, and work in a teamenvironment

·        -Keep up to date with leading edge technologies