Cadence SH 招聘Principal/Lead IP design Engineer

kengteng

Cadence SH 招聘Principal/LeadIP design Engineer

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Title：Principal/LeadIP design Engineer

Position Description:

1.Performphysical design implementation, including synthesis, floor planning, power griddesign, place and route, clock tree synthesis, timing closure, power/signalintegrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFMClosure, and physical design project management.

2.Thecandidate will have the opportunity to work on many varieties of challengingdesigns, i.e. low power and high speed design. The responsibility includesparticipating in or leading next generation physical design, methodology andflow development.

Position Requirements:

1.BS degree with 6~10+ years of applicableexperience, MS degree with 4~7+ years of applicable experience in electricalengineering, microelectronics.

2. Experienced with asic design flow,hierarchical physical design strategies, and methodologies and understand deepsub-micron technology issues. Solid knowledge on LP Design, DFT, static timinganalysis, EM/IR-Drop/crosstalk analysis, formal verification, physicalverification, DFM.

3.Successfultrack records of taping out complex, 65/40/28 nm SOC chips.

4.Automation and programming-minded, solidcoding experience in Makefile/Tcl/Tk/Perl.

5.Self-motivated, able to work independently oras a team player

6.Excellent verbal and written communicationskills in English.