马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
smic13g 库内cell (NAND2X1) {
cell_footprint : nand2;
area : 5.092200;
pin(A) {
direction : input;
capacitance : 0.002978;
}
pin(B) {
direction : input;
capacitance : 0.002803;
}
pin(Y) {
direction : output;
capacitance : 0.0;
function : "(!(A B))";
csmc018_max库内
cell (nd02d1) {
cell_leakage_power : 354.735;
leakage_power () {
value : 197.608;
when : "A&B";
}
leakage_power () {
value : 478.824;
when : "A&!B";
}
leakage_power () {
value : 580.559;
when : "!A&B";
}
leakage_power () {
value : 161.949;
when : "!A&!B";
}
area : 0.75;
cell_footprint : "nd02d";
pin (Y) {
direction : output;
function : "(!(B&A))";
.13库里NAND面积比.18库里NAND面积还要大?虽然不是一家的库,但是怎么会这么离谱?请各位前辈不吝赐教~~~~~
另外我用DC求工程所用门数的方法是下面这个方法,对吗?
‘To get the equivalent gate area in Design compiler need to add two comamnds in TCl script. 1. First to get the total area of your design, use report_area.
2. Then divide this area by the area for a 2-input NAND gate in your technology library. You can also use the following command to find out the area for a 2-input nand gate.
dc_shell-xg-t> get_attribute { technology library/2_input_nand_gate_name } area
to get the 2_input_nand_gate_name, use report_lib <tecnology_lib > and select the any drive strength. Usually its 1x drive strength.
Area = $report_area/Area_of nand gate’ |