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本人最近在研究UVM,尝试搭一个AHB RAM的验证环境,但是在设置transfer循环次数的时候sequence里面没法接收参数,我完全是参照uvm1.1中那个ubus的例子在做,烦请各位帮忙看下有什么问题
class ahb_test extends uvm_test;
`uvm_component_utils(ahb_test)
ahb_env t_env ;
function new (string name="ahb_test", uvm_component parent=null);
super.new (name, parent);
t_env = new("t_env",this);
endfunction : new
virtual function void build_phase(uvm_phase phase);
uvm_config_db#(int)::set(this, "t_env.ahb_mseqr.ahb_master_sequence","num_trans",2);
uvm_config_db#(uvm_object_wrapper)::set(this,"t_env.ahb_mseqr.main_phase",
"default_sequence", ahb_master_sequence::type_id::get());
......
endfunction
endclass
class ahb_master_sequence extends uvm_sequence #(ahb_master_transaction);
int num_trans = 1;
function new(string name="ahb_master_sequence");
super.new(name);
endfunction
`uvm_object_utils(ahb_master_sequence)
ahb_master_transaction ahb_m_tr;
virtual task body();
if(!(uvm_config_db#(int)::get(null,get_full_name(),"num_trans", num_trans)));
`uvm_info("No transaction fed:",{get_full_name(), " use default num_trans"}, UVM_LOW);
uvm_report_info(get_full_name(),"Start transfering...",UVM_LOW);
for(int i=0; i<num_trans; i++)
`uvm_do(ahb_m_tr);
endtask
endclass
运行的时候得到这个
UVM_INFO ../tb/ahb_master_sequence.sv(15) @ 0: uvm_test_top.t_env.ahb_mseqr@@ahb_master_sequence [No transaction fed:] uvm_test_top.t_env.ahb_mseqr.ahb_master_sequence use default num_trans
UVM_INFO @ 0: uvm_test_top.t_env.ahb_mseqr@@ahb_master_sequence [uvm_test_top.t_env.ahb_mseqr.ahb_master_sequence] Start transfering...
请问怎么回事呢?非常感谢 |
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