- Understand the architecture of the chip and functional block being designed
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/us
e the automated regression infrastructure setup for unit level, IP level and f
ull chip functional verification.
- Help debug and correct functional errors in the design blocks, using logic a
bstraction, simulation and debug tools, based on good understanding of the arc
hitectural specification, RTL and/or device level design of the block.
- Closely working with Design/Architecture/Circuit team to identify the Milest
ones and Quality metrics of the project that includes scoping, tracking and de
livery.
- Be responsible to mentor and coach the team for greater technical depth in F
unctional areas as well as the verification methodology improvement and Infras
tructure enhancements to support the design environment
Preferred Experience:
- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+
years working experiences
- Should be versatile in any one of the high level verification flow such as S
V,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verific
ation
- Needs to have better understanding of Verification methodology and concepts.
- Should have good understanding of Pre-Silicon design process from Architectu
re, Design, Synthesis and Gate level Implementation till Tapeout release.
- Should have excellent communication skills (both written and oral) and shoul
d be able to participate cross functional engineering teams geographically.
- Familiar with Linux Environment (including shell scripting and linux gnu too
ls)
- Advanced programming knowledge on Verilog,C++
- Design for verification (assertion based design strategies, code coverage, f
unctional coverage, test plan, gate-level simulation, back-annotation etc.)
- Strong problem solving skills