[全职]AMD上海热招职位列表

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1. SMTS Gpahics IP Low power design and verification

Job Summary:

GFXIP Low power design and verification

Job Responsibilities:

In this key role, the candidate will be responsible for low power implementation and verification of Graphics hardware

Development of infrastructure for verification of hardware in GFX IP.

Develop low power verification environments for feature test, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.

Low power design and verification for specific hardware functionality in Front-end.

Improve the low power IP delivery for variant SoCs

Education& Qualifications:

BS, MS or PhD in Electrical Engineering or Computer Science.

10+ years of ASIC verification or low power design/verification experience

UPF based low power design/verification or computer graphics knowledge are plus

Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till tapeout release.

Advanced programming knowledge on Verilog/SystemVerilog, C/C++

Requires demonstrated technical expertise in the areas of low power design/verification methodology.

Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.

Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.

2.
Senior ASIC CAD engineer

1.
Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.

2.
Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products

3.
Technical support and programming

4.
Interface with EDA venders on technology

Requirements:

1.
Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences

2.
Good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow

3.
Must have equivalence check experience

4.
Experience in ASIC design (digital design, Front-end and/or Back-end)

5.
Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route) and usage of related EDA tools

6.
Good written and spoken English

7.
Good communication skills and be able to work both independently and in a team

Highlight:

1.
The key requirement is experience with UPF :

UPF2.0 preferred but UPF1.0 is acceptable

DC-T power aware synthesis

MVRC checking on RTL used for synthesis and especially on netlist after synthesis

Formality – both power aware with UPF and non-power aware

2.
Hands on DFT implementation experience:

DFT scan implementation using Mentor Testkompress (short term need) or Synopsys DFTMAx (long tern need)

Understanding of scan compression logic generation and stitching of this logic into the design

Understanding of Isolation wrappers for scan

3. Senior graphics driver engineer

DESCRIPTION OF DUTIES:

- Develop and maintain the AMD GPU Graphics Driver

- Work with ASIC design team to tune Graphics Driver performance

PREFERRED EXPERIENCE:

- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineerin

g

- 3+ years of experience of graphics driver development is a plus

- 3+ years of experience of C/C++ programming

- Knowledge of Graphics application developing under Microsoft Windows/Linux

- Knowledge of Computer Graphics

- Knowledge of x86 assembler language and x86/x64 CPU instructions

- Knowledge of PC architecture

4. Design Verificaiton Engineer(该职位倾向于毕业三年以下比较年轻有培养潜力的工

程师)

Key Job Functions:

- Understand the ASIC design/verification flow and help design/verification en

gineers to accomplish targets.

- Develop infrastructure and environment for SOC/IP level chip design verifica

tion.

- Closely working with Design/Architecture/Verification team to develop new ve

rification flow.

Preferred Experience:

- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+

years working experiences

- Familiar with Linux Environment (including command shell scripting)

- Skillful at script language like ruby, perl, or tcl

- Be good at C/C++ programming

- Should be versatile in any one of the high level verification flow such as S

V,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verific

ation

- Should have excellent communication skills (both written and oral)

- Strong problem solving skills

- Good knowledge on verification methodology

5.Senior graphics IP Verification Engineer

- Understand the architecture of the graphics IP and functional block being de

signed

- Build C/C++ model for simulation

- Build test bench and monitors for DUT

- Compose test plan and validation vectors to ensure functional completeness

- Debug function/performance bugs of graphics IP

Preferred Experience:

- Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 4+

years working experiences

- Familiar with Linux Environment (including shell scripting and linux gnu too

ls)

- Experience with design for verification (assertion based design strategies,

code coverage, functional coverage, test plan, gate-level simulation, back-ann

otation etc.)

- Should be versatile in any one of the high level verification flow such as S

V,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verific

ation

- Should have excellent communication skills (both written and oral)

- Strong problem solving skills

5. MTS Design Verification Engineer for Graphics HW

Key Job Functions:

- Understand the architecture of the chip and functional block being designed

- Compose test plan and validation vectors to ensure functional completeness

- Develop verification environments for standalone unit testing and enhance/us

e the automated regression infrastructure setup for unit level, IP level and f

ull chip functional verification.

- Help debug and correct functional errors in the design blocks, using logic a

bstraction, simulation and debug tools, based on good understanding of the arc

hitectural specification, RTL and/or device level design of the block.

- Closely working with Design/Architecture/Circuit team to identify the Milest

ones and Quality metrics of the project that includes scoping, tracking and de

livery.

- Be responsible to mentor and coach the team for greater technical depth in F

unctional areas as well as the verification methodology improvement and Infras

tructure enhancements to support the design environment

Preferred Experience:

- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+

years working experiences

- Should be versatile in any one of the high level verification flow such as S

V,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verific

ation

- Needs to have better understanding of Verification methodology and concepts.

- Should have good understanding of Pre-Silicon design process from Architectu

re, Design, Synthesis and Gate level Implementation till Tapeout release.

- Should have excellent communication skills (both written and oral) and shoul

d be able to participate cross functional engineering teams geographically.

- Familiar with Linux Environment (including shell scripting and linux gnu too

ls)

- Advanced programming knowledge on Verilog,C++

- Design for verification (assertion based design strategies, code coverage, f

unctional coverage, test plan, gate-level simulation, back-annotation etc.)

- Strong problem solving skills