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574920045

WARNINGlace:837 - Partially locked IO Bus is found.
WARNINGlace:1206 - This design contains a global buffer instance,
   <u_pll_top/clkout1_buf>, driving the net, <clk>, that is driving the
   following (first 30) non-clock load pins off chip.
   < PIN: sdramsdr_CLK.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was
   applied on COMP.PIN <u_pll_top/clkout1_buf.O> allowing your design to
   continue. This constraint disables all clock placer rules related to the
   specified COMP.PIN.
WARNINGlace:1206 - This design contains a global buffer instance,
   <u_WRfifo/u_pll_sub/clkout1_buf>, driving the net, <u_WRfifo/RCLK>, that is
   driving the following (first 30) non-clock load pins off chip.
   < PIN: TXCA.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was
   applied on COMP.PIN <u_WRfifo/u_pll_sub/clkout1_buf.O> allowing your design
   to continue. This constraint disables all clock placer rules related to the
   specified COMP.PIN.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <u_pll_top/clkout1_buf>, driving the net,
   <clk>, that is driving the following (first 30) non-clock load pins.
   < PIN: sdramsdr_CLK.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <u_pll_top/clkout1_buf.O> allowing your design to continue. This constraint
   disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1137 - This design is not guaranteed to be routable! This design
   contains a global buffer instance, <u_WRfifo/u_pll_sub/clkout1_buf>, driving
   the net, <u_WRfifo/RCLK>, that is driving the following (first 30) non-clock
   load pins.
   < PIN: TXCA.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. Please pay extra attention to the timing and routing of this path to
   ensure the design goals are met. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <u_WRfifo/u_pll_sub/clkout1_buf.O> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
WARNING:Place:1112 - Unroutable Placement! A BUFIO / PLL clock component pair
   have been found that are not placed at a routable BUFIO / PLL site pair. The
   BUFIO component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0> is placed at site
   <BUFIO2_X3Y10>. The corresponding PLL component
   <u_WRfifo/u_pll_sub/pll_base_inst/PLL_ADV> is placed at site <LL_ADV_X0Y1>.
   The BUFIO can use the fast path between the BUFIO and the PLL if the BUFIO is
   in TOPor BOTTOM edge and both the BUFIO & PLL are placed in the same half of
   the device (TOP or BOTTOM). This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK> allowing your design to continue.
   This constraint disables all clock placer rules related to the specified
   COMP.PIN. This placement is UNROUTABLE in PAR and therefore, this error
   condition should be fixed in your design.
WARNING:Place:1139 - Unroutable Placement! A BUFIOFB / PLL clock component pair
   have been found that are not placed at a routable BUFIOFB / PLL site pair.
   The BUFIOFB component <SP6_INS_BUFIO2FB_PLL_ML_BUFIO2FB_2> is placed at site
   <BUFIO2FB_X3Y10>. The corresponding PLL component
   <u_WRfifo/u_pll_sub/pll_base_inst/PLL_ADV> is placed at site <LL_ADV_X0Y1>.
   The BUFIOFB can use the fast path between the BUFIOFB and the PLL if the
   BUFIOFB is in TOPor BOTTOM edge and both the BUFIOFB & PLL are placed in the
   same half of the device (TOP or BOTTOM). This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
   <SP6_INS_BUFIO2FB_PLL_ML_BUFIO2FB_2.O> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
   This placement is UNROUTABLE in PAR and therefore, this error condition
   should be fixed in your design.