New Synplify Features and Benefits | Synplify Pro® | Synplify® Premier |
Improved runtimes and turnaround
Option to now read Xilinx® Structural Verilog files and pass on to place and route intact
Faster incremental compilation
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Improved Vivado® productivity
“Quick start” constraints file generator - create_fdc_template | | |
High performance and great area QoR without runtime tradeoff
Faster runtimes for large 20-nm devices - Altera® Arria® 10 and Xilinx UltraScale | | |
Easier ASIC conversion with design diagnostics and feedback earlier in synthesis
More intuitive constraints setting and reporting
Verilog Force/Bind for faster debug, greater source compatibility with simulation and ASIC design conversion
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Improved QoR for Xilinx and Altera including DSP memory-intensive designs
Enhanced dual-port byte enabled RAM inferencing and DSP inferencing
5% Xilinx QoR improvement for HAPS-70/DX and any Virtex®-7 design by using the new “Advanced Synthesis” option
Early resource estimation and control for clocks, memories and DSPs | | ✓
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More high-reliability design automation
Support for safe FSMs with negedge clock
Safe FSM enhancements allow you to choose any major state encoding algorithm | | |
DSP design productivity
New DSP blocksets for CORDIC and MATH functions | | |