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发表于 2014-6-21 09:56:23
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本帖最后由 baddy2323 于 2014-6-21 10:08 编辑
回复 1# ma1970
部分log文件
8:45:16 (lmgrd) lmgrd tcp-port 5280
8:45:16 (lmgrd) Starting vendor daemons ...
8:45:16 (lmgrd) Started cdslmd (internet tcp_port 39846 pid 6072)
8:45:16 (cdslmd) FLEXnet Licensing version v10.8.2.1 build 30341
8:45:18 (cdslmd) Server started on ubuntu for: 100
8:45:18 (cdslmd) 111 11300 11400
8:45:18 (cdslmd) 11701 11702 11703
8:45:18 (cdslmd) 11710 12110 12111
8:45:18 (cdslmd) 12121 12141 12141_64bit
8:45:18 (cdslmd) 12150 12500 14000
8:45:18 (cdslmd) 14010 14020 14030
8:45:18 (cdslmd) 14040 14060 14100
8:45:18 (cdslmd) 14101 14110 14111
8:45:18 (cdslmd) 14120 14130 14140
8:45:18 (cdslmd) 14400 14410 14420
8:45:18 (cdslmd) 200 20120 20121
8:45:18 (cdslmd) 20122 20123 20124
.................
8:45:18 (cdslmd) actomd ADE_ElectronStorm_Option ADE_VoltageStorm_Option
8:45:18 (cdslmd) ADV_2S10PUC_ALL ADV_2S15PUC_ALL ADV_2S20PUC_ALL
8:45:18 (cdslmd) ADV_2S40PUC_ALL ADV_2S60PUC_ALL ADV_2SUPUC_ALL
8:45:18 (cdslmd) ADV_4S10PUC_ALL ADV_4S20PUC_ALL ADV_4S40PUC_ALL
8:45:18 (cdslmd) ADV_4S60PUC_ALL ADV_4SUPUC_ALL ADV_6S60PUC_ALL
8:45:18 (cdslmd) ADV_6S90PUC_ALL ADV_6SUPUC_ALL Advanced_Cell_Placer
8:45:18 (cdslmd) advanced_package_designer Advanced_Pkg_Engineer_3D adv_package_designer_expert
8:45:18 (cdslmd) adv_package_engineer_expert Affirma_3rdParty_Sim_Interface Affirma_advanced_analysis_env
8:45:18 (cdslmd) Affirma_AMS_distrib_processing Affirma_ams_simulator Affirma_equivalence_checker
8:45:18 (cdslmd) Affirma_equiv_checker_prep Affirma_model_checker Affirma_model_packager_export
8:45:18 (cdslmd) Affirma_NC_Simulator Affirma_NC_VHDL_Desktop_Sim Affirma_RF_IC_package
8:45:18 (cdslmd) Affirma_RF_IC_package_modeler Affirma_RF_SPW_model_link affirma-signalscan
8:45:18 (cdslmd) affirma-signalscan-control affirma-signalscan-pro affirma-signalscan-schmatic
8:45:18 (cdslmd) affirma-signalscan-source affirma-signalscan-transaction Affirma_sim_analysis_env
8:45:18 (cdslmd) Affirma_transaction_analysis affirma-transaction-explorer Affirma_trans_logic_abstracter
8:45:18 (cdslmd) ALL_EBD Allegro_CAD_Interface Allegro_Design_Editor_620
8:45:18 (cdslmd) Allegro_Designer Allegro_designer_suite Allegro_design_expert
8:45:18 (cdslmd) allegro_dfa allegro_dfa_att Allegro_Expert
8:45:18 (cdslmd) Allegro_Librarian allegro_non_partner Allegro_Package_Designer_620
8:45:18 (cdslmd) Allegro_Package_SI_620 Allegro_Package_SI_620_Suite Allegro_PCB
8:45:18 (cdslmd) Allegro_PCB_Design_230 Allegro_PCB_Design_620 Allegro_PCB_Interface
8:45:18 (cdslmd) Allegro_PCB_Partitioning Allegro_PCB_RF Allegro_PCB_Router_210
8:45:18 (cdslmd) Allegro_PCB_Router_230 Allegro_PCB_Router_610 Allegro_PCB_SI_230
8:45:18 (cdslmd) Virtuoso_Core_Optimizer Virtuoso_custom_placer Virtuoso_custom_router
8:45:18 (cdslmd) Virtuoso_Digital_implement Virtuoso_Layout_Migrate Virtuoso_Layout_Suite_GX
8:45:18 (cdslmd) Virtuoso_Layout_Suite_GXL Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL
8:45:18 (cdslmd) Virtuoso_Multi_mode_Simulation Virtuoso_NeoCircuit_DFM Virtuoso_Phase_Designer
8:45:18 (cdslmd) Virtuoso_QRC_Extraction_GXL Virtuoso_QRC_Extraction_L Virtuoso_QRC_Extraction_XL
8:45:18 (cdslmd) Virtuoso_Schematic_Editor_GXL Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL
8:45:18 (cdslmd) Virtuoso_Schem_Option Virtuoso_SiI VIRTUOSO_SPEC_DRIVEN_ENVIRO
8:45:18 (cdslmd) Virtuoso_Spectre Virtuoso_Spectre_GXL Virtuoso_Spectre_RF
8:45:18 (cdslmd) Virtuoso_Spectre_XL Virtuoso_Sprectre_GXL_MMSIM_LK Virtuoso_Turbo
8:45:18 (cdslmd) Virtuoso_Turbo_Basic Virtuoso_Visual_Analysis_XL Virtuoso_XL
8:45:18 (cdslmd) Virtuoso_XL_Basic visula_in VITAL-XL
8:45:18 (cdslmd) vloglink vmanager VoltageStorm_Cell_Transistor2
8:45:18 (cdslmd) VoltageStorm_UI VXL-ALPHA VXL-LMC-HW-IF
8:45:18 (cdslmd) VXL-SWITCH-RC VXL-TURBO VXL-VCW
8:45:18 (cdslmd) VXL-VET VXL-VLS VXL-VRA
8:45:18 (cdslmd) wedifsch WinPlace WireEdit
8:45:18 (cdslmd) WLAN_Simulation_Runtime X4ENC xilCds
8:45:18 (cdslmd) xilComposerFE xilConceptFE xilEdif
8:45:18 (cdslmd) Xilinx_FPGA
8:45:18 (cdslmd)
8:45:18 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
8:45:18 (cdslmd)
8:45:18 (cdslmd)
8:45:18 (lmgrd) cdslmd using TCP-port 39846
8:46:45 (cdslmd) TCP_NODELAY NOT enabled
8:46:45 (cdslmd) OUT: "Affirma_sim_analysis_env" baddy2323@ubuntu
8:46:45 (cdslmd) IN: "Affirma_sim_analysis_env" baddy2323@ubuntu
8:46:49 (cdslmd) OUT: "Affirma_sim_analysis_env" baddy2323@ubuntu
8:46:49 (cdslmd) IN: "Affirma_sim_analysis_env" baddy2323@ubuntu
baddy2323@ubuntu:~$ simvision &
[1] 7877
baddy2323@ubuntu:~$ simvision: 13.20-p002: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
*F,LCFAIL: (LM -8) Unable to obtain a license for version 13.2
of feature 'Affirma_sim_analysis_env' in any license file
(run 'lic_error -8' for more information)
baddy2323@ubuntu:/tools/cadence/license# lmstat -a -c cadence.dat,部分显示
Users of lwb: (Uncounted, node-locked)
Users of MAG_LIB: (Uncounted, node-locked)
Users of mdin: (Uncounted, node-locked)
Users of mdout: (Uncounted, node-locked)
Users of mdtoac: (Uncounted, node-locked)
Users of mdtocv: (Uncounted, node-locked)
Users of MIXAD_LIB: (Uncounted, node-locked)
Users of Model_Check_Analysis: (Uncounted, node-locked)
Users of MSMV: (Uncounted, node-locked)
Users of Multithread_Route_Option: (Uncounted, node-locked)
Users of multiwire: (Uncounted, node-locked)
Users of MV_4S40PUC_ALL: (Uncounted, node-locked)
Users of MV_6SUPUC_ALL: (Uncounted, node-locked)
Users of Nano_Encounter: (Uncounted, node-locked)
Users of Nano_Encounter_DBS: (Uncounted, node-locked)
Users of NanoRoute_Ultra: (Uncounted, node-locked)
Users of NCSim_Desktop: (Uncounted, node-locked)
Users of NC-simulator: (Uncounted, node-locked)
Users of nc_specman: (Uncounted, node-locked)
Users of ncsysc_specman: (Uncounted, node-locked)
Users of NC_SystemC_Simulator: (Uncounted, node-locked)
Users of NC_SystemVerilog_Simulator: (Uncounted, node-locked)
Users of NC_Verilog_Compiler: (Uncounted, node-locked)
工具iscape安装后面弹出的我全点回车或yes，有影响没？ 看上个帖子什么的nodelock啊
这应该是已经破解了把，为啥我取不到License呢，帮帮忙。 |
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