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1.
Senior synthesisexpert Responsibilities: Develop, maintain andsupport FPGA synthesis tools Education: MS or above in EE, CS or relatedfields Skills: -
excellent C++programming skill, -
familiar with EDAtools and FPGA design methodology -
complete anddetailed knowledge and skills in logic synthesis, logic optimization and logicmapping -
fluent in applyingcombinatorial optimization algorithms and techniques in solving synthesisproblems -
familiar withtiming driven logic synthesis -
familiar withVerilog and VHDL
Experiences: -
10+ yearsexperiences in ASIC or FPGA synthesis. -
experience inLUT-based FPGA synthesis is preferred -
experience indeveloping and maintaining complex large software -
experience in FPGAsoftware development and productization -
experience insolving customers’ issue
2.
Senior Placementexpert Responsibilities: Develop, maintain andsupport FPGA placement tools Education: MS or above in EE, CS orrelated fields Skills: -
excellent C++programming skill, -
familiar with EDAtools in placement and routing -
complete anddetailed knowledge and skills in ASIC/FPGA timing-driven placement; includingglobal placement, detailed placement and floor-planning -
fluent in applyingcombinatorial optimization algorithms and techniques in solving placementproblems -
familiar withtiming estimation -
familiar withquality of results improvement methods and procedures
Experiences: -
10+ years hands-onexperiences in ASIC or FPGA placement -
experiences inLUT-based FPGA placement and floor-planning is preferred -
experiences indeveloping and maintaining complex large software -
experiences inFPGA software development and productization -
experiences inactually improving quality of results of a design
3.
Senior Routingexpert Responsibilities: Develop, maintain and supportFPGA routing tools. Education: MS or above in EE, CS orrelated fields Skills: -
excellent C++programming skill, -
familiar with EDAtools in placement and routing -
complete anddetailed knowledge and skills in FPGA routing. -
fluent in applyingcombinatorial optimization algorithms and techniques in solving routing -
strong knowledgein graph algorithms -
familiar with timingdriven routing tools development
Experiences: -
10+ years hands-onexperiences in FPGA or ASIC routing. -
experience inLUT-based FPGA routing is preferred -
experience inanalyze and solve routing failures in FPGA designs -
experience in FPGAsoftware development and productization -
4.
Senior Timingexpert Responsibilities: Develop, maintain andsupport all timing needs for FPGA products. Education: MS or above in EE, CS orrelated fields Skills: -
excellent C++programming skill, -
familiar with EDA timingtools, and industrial standard timing and power data formats -
complete anddetailed knowledge and skills in timing prediction, estimation, measurement andcorrelation -
familiar withstatic timing analysis analysis
Experiences: -
10+ years hands-onexperiences in IC timing analysis, preferably FPGA. -
experience in FPGAtiming analysis and timing data correlation is preferred -
experience indeveloping and maintaining static timing analysis engine -
experience in analyzeand solve timing failures in FPGA designs -
experience inpower analysis in FPGA is preferred
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发表于 2014-4-29 15:30:42
