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Sr. PHYSICALDESIGN ENGINEER DESCRIPTION: A senior role in physical design forNVIDIA GPU and Mobile chips Participate in various aspects ofphysical design, including full chip floorplanning, power/clock distribution,timing optimization, place & route, timing closure, power/signal integrityanalysis, and physical verification Troubleshoot a wide variety of design andflow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuitdesigners to ensure the high quality of design implementation and optimization MINIMUMREQUIREMENTS: -
BS in Engineering or Science -
Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC),Cadence (EDI/EPS) or Mentor (Olympus-SOC) -
Experience in Clock/Power Distribution,P&R, Timing closure, RC Extraction,and verification on 40nm, or 28nm technology -
3+ years of experience in above areas PREFERRED: -
MSin Engineering or Science -
Knowledgein 20nm or FinFET technology, circuit design, and package design -
Experiencein physical verification tools from Synopsys (ICV/Mojave) or Mentor (Calibre) -
Proficiencyin Perl, TCL and Makefile scripts
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发表于 2014-4-24 10:11:32
