Cadence Korea 招聘职位若干

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Cadence Korea 招聘职位

Ifyou have interest, PLS send your update CV to job_china@cadence.com

1.Staff Product Engineer / Principal Product Engineer / Sr. Product Engineer            

            

PositionDescription:   

1. Candidate is required to workwith customers and foundries to support advanced node projects specifically inthe area of RTL-2-GDS implementation or part of it.

2. Work involves working with Keycustomers, executing to their specifications and in process help cadencevalidate the tools for advanced node as well as future node challenges.

PositionDescription:                           

1. Candidate should have at least7 years of ASIC Design based RTL-2-GDS flow implementation experience. Overallexperience should be at least 15 years.

2. Candidate should have aBachelor or Master’s degree in electronics or equivalent

3. Should have good command onscripting skills such as Perl & Tcl.

4. Should have high expertise inthe area of RTL to gds implementation with Industry standard tools &methodologies which includes synthesis, placement, CTS, routing and physicalverification.

5. Should have good communicationskills to be able to effectively communicate internally and externally withcustomers.

2.Principal Application Engineer- Samsung/ASIC Team

PositionDescription:

1. Work closely with the salesteam to identify and scope opportunities for the Cadence ICD/FED platform.

2. Understand the Goal andObjective, then plan and execute and manage key technical evaluations byco-working proactively with existing and potential customers as well as teamcolleagues

3. Summarize the tasks andprojects, and report to manager and share with team effectively

4. Train, ramp-up and accompanycustomer project.

5. Conduct basic and advancedtrainings, presentations and demos as necessary.

6. Ramp-up other members of theteam on the advanced ICD/FED back-end/front-end technologies and tools.

7. Providing technical expertiseto address clients’ queries, which need expert involvement

8. Effective team player, willingto learn

9. Good command of English(written or oral)

PositionRequirements:

1. 10+ years experience indigital IC implementation including synthesis, floorplan, powerplan, placement,CTS, routing, SI & STA signoff.

2. Hands-on experience on running0.13um / 90nm hierarchical, timing driven, SI prevention, low powerplace-and-route projects a big plus

3. Familiar with logic synthesis(DC or RC), P&R implementation (ICC or EDI), STA (ETS/Tempus orPrimeTime-SI), RC extraction, LEF generation with Abstract generator

4. Knowledge of Linux and tcl isa must

5. Good program / engagement managementskill

6. Effective team player, willingto learn

7. Good command of English(written or oral)

3.Principal Application Engineer - IP

PositionDescription:

Responsibilities include:

1. Providing direct technicalsupport to customers in presale stage to persuade customers to adopt CadenceAMS IP solutions for their applications

2. Interface with customerarchitects and AMS IP business unit to enable evaluation of applicationspecific IP performance and features per customer’s SOC requirements.

3. Working with the sales team tomanage the IP activities in the region to achieve a high customer satisfactionrate and for building strong customer relationships

4. Providing customer feedback onnew/existing requirements for AMS IP usage from customers to the R&Dbusiness unit.

5. Providing direct technicalcustomer support and assistance to enable customers to successfullyintegrate/use AMS IP in their SOC.

6. Writing application notes andreview protocol specifications for AMS IP

PositionRequirements:

1. Experience in AMS design andarchitecture development.

2.  Experience with SOC architecture and highspeed protocols.

3.  Exposure to IP-based SOC design flow and realtape-out experience.

4.  Good written and verbal communication skillsand problem solving skills are required.

5.  Ability to conduct technical meetings,presentations, seminars and training to customers and to the sales team

6. Travel within AP region may berequired.

7. Good understanding of thesemiconductor IP marketplace and ecosystem is a plus.