altera自动生成PCIE模型综合分布引脚出错

leebt

有没有人ALTERA自动生成PCIE，本人在生成完模型后，综合发现默认指定的pin脚信息综合出错，但是根据参考手册上说的该引脚应该可以使用的，百思不得其解，希望做个的大侠给个指导意见，不甚感谢！！！以下是综合出错信息。3 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins.
    Info (184026): differential I/O pin "PCIE_TX" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "PCIE_TX(n)".
    Info (184026): differential I/O pin "PCIE_CLK" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "PCIE_CLK(n)".
    Info (184026): differential I/O pin "PCIE_RX" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "PCIE_RX(n)".
Error (175020): Illegal constraint of Receiver channel to the region (0, 12) to (0, 14): no valid locations in region
    Info (175028): The Receiver channel name: PCIE_RX
    Info (175015): The I/O pad is constrained to the location PIN_AJ2 due to: User Location Constraints (PIN_AJ2)
Error (12289): An error occurred while applying the periphery constraints.