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Sr. Staff verification engineer (绝对高大上的公司
高大上的验证机会不容错过) Job Area Engineering - Verification Location China - Shanghai
Job Function Job Description Define verification infrastructure using SystemVerilog, Formal and UVM. Assist in complete verification of highperformance, high feature, low power ASIC. Work closely with system architect and designmanagers to architect a new design verification environment and produce highquality verification closure. Guide the development of comprehensive, flexible,and portable block to chip level test-benches, detail test plans and coverageclosure. Expert in industry standards such as PCIe, USB,Ethernet, 802.3, 802.11, ARM, etc. wifi Infrastructure work including developing scripts,methodologies and tools for efficiency and quality improvements.
Job Requirements 2
Strong verification and technical lead skillsincluding a good knowledge and understanding of different verificationmethodologies: 2
architecture vs micro-architecture level 2
random vs directed testing 2
fullchip vs module-level 2
performance vs function 2
error & drop handling 2
Past experience of successfully technicallyguiding complex, multi-million gates, high speed design verification. 2
Experience with the following areas in design andverification: 2
Advanced Constrained-random functionalverification methodology such as OVM/UVM/VMM and/or SV Assertion. 2
Systems using communication systems/protocolssuch as 802.3, PCIe, USB3, AXI, 802.11, ARM and NoC. 2
Formal verification with abstraction model forend-to-end checking. 2
Low power verification with power gating andpower management. 2
Debug methodology 2
Self-motivated, good communicator, quick learnerand good team player. 2
Display positive attitude and demonstrateflexibility in day-to-day work. 2
MS/EE or CS with 12-16 years of relevantexperience.
Grace Li @ Hi-Talent Consulting Co. , Ltd. 上海芯相会企业管理咨询有限公司 上海芯得企业管理咨询有限公司 E-Mail: bestgrace@qq.com QQ: 2862465331 新浪blog:http://blog.sina.com.cn/u/1767088102
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