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*Novas* End of traversing the scope(tb_chip)
driver initialization ok!
Doing SDF annotation ...... Done
Test begin!
*******************************************************************
the testname is 00000003
*******************************************************************
theHH BTA_END is 163122300
"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4437: Timing violation in tb_chip.U_impro.U_ddr3_top.U_tx_phy.data_out_n_reg
$setuphold( posedge CK &&& (flag == 1'b1):177498792, posedge D:177498700, limits: (100,50) );
"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4438: Timing violation in tb_chip.U_impro.U_ddr3_top.U_tx_phy.cmd_out_n_reg
$setuphold( posedge CK &&& (flag == 1'b1):177498792, negedge D:177498700, limits: (100,50) );
"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4437: Timing violation in tb_chip.U_impro_chip.U_ddr3_top.U_tx_phy.div_en_cnt_reg_1_
$setuphold( posedge CK &&& (flag == 1'b1):177498792, posedge D:177498700, limits: (100,50) );
以上是simulation 中的warning
----------------------------------------------------------------------------------------------------------------
(CELL
(CELLTYPE "DFFRDL")
(INSTANCE U_tx__phy/data_out_n_reg)
(DELAY
(ABSOLUTE
(IOPATH RB Q () (0.997::0.997))
(IOPATH RB QB (0.884::0.884) ())
(IOPATH (posedge CK) Q (1.229::1.229) (0.848::0.848))
(IOPATH (posedge CK) QB (0.736::0.736) (1.123::1.123))
)
)
(TIMINGCHECK
(WIDTH (negedge RB) (::1.687))
(WIDTH (posedge CK) (::0.375))
(WIDTH (negedge CK) (::0.544))
(SETUPHOLD (posedge D) (posedge CK) (::0.271) (::-0.232))
(SETUPHOLD (negedge D) (posedge CK) (::0.208) (::-0.038))
(RECREM (posedge RB) (posedge CK) (::0.315) (::-0.278))
)
)
这个是sdf 中对应的Timingcheck 部分。
我从simulation 的 warning (红色部分)中觉得sdf的timing check 没效果,好像有的是仿真库文件中的值 ,但是编译过程sdf 反标的log中没有看到error, 也显示了反标结束, sdf 反标的warning中没有关于上面几个寄存器的内容。 我第一次搭建后仿真环境,不知道有什么地方出了问题,希望各位大神指点一下
反标过程中的warning,基本上是 negtive value cannot handle by the switch -negdelay |
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