上海顶级外资Q公司招聘资深（staff or senior staff）验证工程师

liu_uestc

欢迎联系
qq: 2492202119
email: liu_uestc@163.com
Job Area
Engineering - Verification
Location China - Shanghai
Job Function
Job Description
Define verification infrastructure using System Verilog, Formal and UVM.
Assist in complete verification of high performance, high feature, low power ASIC.
Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure.
Guide the development of comprehensive, flexible, and portable block to chip level test-benches, detail test plans and coverage closure.
Expert in industry standards such as PCIe, USB, Ethernet, 802.3, 802.11, ARM, etc.
Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Job Requirements
Strong verification and technical lead skills including a good knowledge and understanding of different verification methodologies:
oarchitecture vs micro-architecture level
orandom vs directed testing
ofullchip vs module-level
operformance vs function
oerror & drop handling
Past experience of successfully technically guiding complex, multi-million gates, high speed design verification.
Experience with the following areas in design and verification:
oAdvanced Constrained-random functional verification methodology such as OVM/UVM/VMM and/or SV Assertion.
oSystems using communication systems/protocols such as 802.3, PCIe, USB3, AXI, 802.11, ARM and NoC.
oFormal verification with abstraction model for end-to-end checking.
oLow power verification with power gating and power management.
oDebug methodology
Self-motivated, good communicator, quick learner and good team player.
Display positive attitude and demonstrate flexibility in day-to-day work.
MS/EE or CS with 12-16 years of relevant experience.