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后端-backend engineer [url=mailto:简历发bestgrace@qq.com]简历发bestgrace@qq.com[/url] 15个后端
火速
上海的
北京的 Job Description:
Responsible for physical design implementation of complex SoCs (Netlist-to-GDSII). Work on block level or SoC level physical design in 28nm/20nm technology.
Floorplan, placement, routing, clock tree synthesis, timing closure, signal integrity fixing, DRC/LVS.
Requirements:
- BS, MS, PhD, in computer engineering or electrical engineering
-MUST have at least 2 years of experience in physical design
-Must have successfully taped out at least one complex chip
-Hands on experience with tools like ICC (Synopsys), SocEncounter (Cadence) or Talus (Magma)
-Working knowledge of STA(Primetime), power analysis, DRC/LVS a plus
-Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
-Working knowledge of RTL-to-Netlist such as synthesis, DFT is a plus but not a requirement
-Programming experience in Perl/Tcl a big plus Grace Li @ Hi-Talent Consulting Co. , Ltd. 上海芯相会企业管理咨询有限公司 上海芯得企业管理咨询有限公司 E-Mail: bestgrace@qq.com QQ: 2862465331 新浪blog: http://blog.sina.com.cn/u/1767088102 新浪微博:http://weibo.com/bestgrace Best Regards, Jane.Jin Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd. 上海芯相会企业管理咨询有限公司 上海芯得企业管理咨询有限公司 Mob:
18502155252 Skype:
ScarlettJaneJin E-Mail:
Jane-Jin@Hi-Talent.net QQ:
983144394 Blog:
http://blog.sina.com.cn/u/1716864892 Weibo:
http://weibo.com/u/1716864892 webside:
www.hi-talent.cn |