Silicon-on-Insulator (SOI) and bulk CMOS (RFCMOS) RF

jj_seu · 发表于 2014-1-7 15:49:37

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[url=mailto:简历发offer@hi-talent.net]简历发offer@hi-talent.net[/url]

TD Spice Modeling Engineer/ Snr Engineer
工作地点：上海

Job Purpose:
To develop Silicon-on-Insulator (SOI) and bulk CMOS (RFCMOS) RF transistor model kits for advanced and VAS RF process technologies.

Roles and Responsibilities:

Good understanding of the device physics of SOI and bulk CMOS RF transistors and the correlation of the process technologies to the transistors’ RF performance. The key Figure-of-Merits of interest include Ft, Fmax, 1/f noise, HF noise, IIP3, OIP3, P1dB etc.
Familiar and able to perform DC/AC/RF/noise/large-signal characterization and model extraction of SOI RF transistors using BSIM-SOI and PSP-SOI model architectures in SPECTRE and HSPICE model formats.
Familiar and able to perform DC/AC/RF/noise/large-signal RF characterization and model extraction of bulk CMOS RF transistors using BSIM4.x, BSIM6 and PSP model architectures in SPECTRE and HSPICE model formats.
Able to design and coordinate RF active GSG layouts and device matrices planning for RF modeling testchip development.
Create and maintain testcases for RF transistor models integration into PDK kits, perform simulations and physical quality assurance checks to ensure error free PDK kits delivery to customers. Run customer’s RF transistor testcases/netlists for model QA/de-bugging.
RF transistor scribestreets implementation for statistical RF data monitoring and correlation to RF transistor models variability.
Create and update model release notes, model reference documents and application notes. Document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the RF transistor model kits to customers.

Requirements:
Min. Bachelor Degree in Electrical and Electronics or Microelectronics Engineering.
Software programming skills in UNIX, LINUX and Windows environment.
Hands-on experience with on-wafer DC/AC/RF/noise/large-signal characterization and de-embedding procedures using Cascade Microtech prober, Agilent’s PNA, PLTS etc.
Familiar with RF characterization and modeling softwares such as Agilent’s ICCAP and ADS.
Familiar or has worked on foundry’s PDK and usage for deep submicrometer and/or nanometer testchip tapeouts.
Experience in analog/RF circuit design and/or has performed RF device layouts using Cadence.
Good knowledge of SOI and bulk CMOS semiconductor processes for RF technologies on 28, 40, 55, 65, 130 and 180nm nodes.