新手学习MicroBlaze,添加MPMC时有一个引脚不知道怎么接？

Exiachen

自己学习感觉好吃力。
我用的板子是spartan-3e xc3s500efg320官方开发板。上面有一个Micron的46v32M16的DDR。我在XPS中添加了一个MPMC，网表顺利生成，填好ucf，ucf的填写是根据板子的说明书填的，我觉得引脚名字的大致意思能够对上就连在了一起，结果生成比特文件的时候出错了，ucf文件中有这样一个pin：fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin，我把它连在B9上，出来这样一个错误：Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible. The component type is determined by the types of logic and the properties and configuration of the logic it contains. In this case an IO component of type IOB was chosen because the IO contains symbols and/or properties consistent with output or bi-directional usage and contains no other symbols or properties that require a more specific IO component type. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint.
Summary:
Symbols involved:
     PAD symbol "fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin" (Pad Signal = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin)
     BUF symbol "DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/iobs/controller_iobs/rst_obuf" (Output Signal = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin)
     BUF symbol "DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/iobs/controller_iobs/rst_ibuf" (Output Signal = DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/dqs_div_rst)
Component type involved: IOB
Site Location involved: B9
Site Type involved: DIFFSI
我看了一下fg320的引脚说明，发现B9是时钟：IP_L13N_0/GCLK9。而fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin要求是双向端口，不知道该怎么办了，卡了好久。
后来我将这个pin注释掉，没有连上，生成比特文件的时候却通过了！！
在SDK中写好程序，下载的时候又出来一个错误：
Unexpected error while launching program:  ERROR: Elf Verify failed at Address:
    0x8c00d615
ERROR: Elf Verify failed at Address:
    0x8c00d615
只知道 0x8c00d615是分配给DDR的，觉得应该是DDR的问题，现在彻底不知道该怎么办了。
这两个问题有没有联系？
在此求大神帮忙！！！！！！！！！！！！！！！！！！