synopsys上海FPGA相关职位推荐：IP原型平台验证和flow脚本编写

eaglelsb

有两类职位，一类是IP原型平台验证相关的，USB或PCIE、MIPI相关，这个职位经验丰富点更好，一类是flow流程脚本编写，用bash, perl, tcl之类的编写脚本，两三年经验即可。都属于我现在所在的team，有兴趣的可发简历给我sbliu@synopsys.com


Job Descriptions

1.
This position is responsible for USB protocol FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.  

2.
Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan

3.
Perform FPGA synthesis, define correct timing constraints, IO constraints to achieve time clean synthesis result

4.
Will be involving all states of the prototype development process from the specification define, design implementation, simulation, FPGA synthesis, and hardware system verification.

Position Requirements

1.
BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation.

2.
Must be proficient with Unix OS, Verilog HDL, Perl scripting.

3.
Hardware validation and debugging experiences are highly desirable.

4.
Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus.

5.
Knowledge of the USB3.0/USB2.0/AMBA Protocol or relevant high speed interface protocol (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus.

6.
Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills

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Job Descriptions

1.   Develop and test IP FPGA prototype automation tools, creating the flow/scripts to configure IP core, running Verilog simulation, and FPGA implementation.      

2.   Needs to working with FPGA prototype engineers to understand the IP core configure, verification, FPGA implementation.  Then define the specification of design flow, write scripts to execute. Work with prototype team to improve the design methodologies to help execute prototype project effectively and successfully with high quality

3.  Development infrastructure scripts, such as packing the deliverables, check the completion of release package, screen prototype running log file to generate report, analyze the running result.

Position Requirements

1.
BSEE or MSEE (is preferable) with 3+ yrs of experiences in ASIC/FPGA flow design.

2.
Must be proficient with Unix OS, Verilog HDL, TCL, Perl shell, C/C++

3.   Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus.

4.    Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills

Magee2013

邮箱地址有错误？发不过去/

eaglelsb

回复 2# Magee2013

谢谢提醒，居然打漏了字还没发现，synopsys