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发表于 2014-10-13 20:49:57
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Book DescriptionPublication Date: August 5, 2013 | ISBN-10: 9491216910 | ISBN-13: 978-9491216916 | Edition: 2013
System on chips designs have evolved(发展) from fairly simple unicore, single memory designs to complex heterogeneous(多相的) multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet highcomputational(计算的) demands posed by latest consumer electronic devices, most current systems are based on such paradigm(范例), which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling(强迫). By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional(比例的) to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy(层级), scalable(可攀登的) system interconnect(使互相连接), new programming paradigms, and efficient integration methodology(方法学) for connecting such heterogeneous cores into a single system capable of leveraging(杠杆作用) their individual flexibility(灵活性). Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively(迭代的) map the device’s functionality to a particular HW/SW partition a(划分)nd target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical b(分层的)us, point-to-point c(越过原野的)onnection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled l(重新集合)ater. This reflects the fact that certain processor jobs cannot be easily parallelized t(平行放置)o run concurrently o(兼)n multiple processing cores and that load balancing between processing cores – especially heterogeneous cores – is very difficult. |
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发表于 2014-6-20 21:42:16
