Verilog-AMS Real Valued Modeling Guide

lvzhichong · 发表于 2013-12-4 11:32:31

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Real Valued Modeling (RVM) is a method by which you can perform verification of analog or
mixed-signal designs using discretely simulated real values. This allows simulation using only
the digital solver, avoiding the slower analog simulation and enabling intensive verification of
mixed-signal design within a short period. In this context, you need to consider the trade-off
between simulation performance and accuracy. RVM also opens up the possibility of linkage
with other advanced verification technologies, such as assertion-based verification, without
the difficulty of interfacing with the analog engine ordefining new semantics to deal with the
analog values. It is anticipated that you will enable the RVM flowby migrating your analog
models or transistor-level design to RVM style.

ikon · 发表于 2013-12-30 09:02:51

多谢分享

rockyli · 发表于 2013-12-31 12:04:58

多谢！

paul21st · 发表于 2014-2-17 22:09:37

haodongxi

acer1128 · 发表于 2014-3-13 14:22:11

Real Valued Modeling (RVM) is a method by which you can perform verification of analog or
mixe ...
lvzhichong 发表于 2013-12-4 11:32

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Thx.

virsim · 发表于 2014-3-19 13:00:38

Thx.Thx.

michaeltest · 发表于 2014-4-26 18:08:00

下載學習學習

ra3d · 发表于 2014-11-12 20:12:33

多谢！

joannelin2214 · 发表于 2014-11-12 21:25:03

謝謝!!!!!

tingyc · 发表于 2015-10-21 08:31:12

謝謝!!!!!

[资料] Verilog-AMS Real Valued Modeling Guide

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