1. Experienced ASIC, SOCdesign verification expert with block to chip level verification experience.Familiar with verification flow and worked on testbench, testplan, testexecution and coverage closure, tape out and silicon validation.
2. Hands on experience with oneof the modern verification methodologies such as UVM, VMM, OVM, and familiarwith constraint random based verification, including OOP, functional coverage,assertion checker/coverage and virtual interface.
3. Proficient in HVL(hardwareverification language) such as System Verilog, Verilog, System C or Vera.
4. Knowledge and background innetworking protocols such as Ethernet, PCIe, TCP/IP, Serdes, MAC and PHY arepreferred.
5. Experience on networking ICdesign and verification is preferred, especially ethernet switch, PHY, trafficmanager, network processor, switch fabric and memory sub system projects.
6. The following skills arenot required but under consideration: Perl, TLM, DPI, XACT, XML, PHP, mySQL.
7. Emulation, FPGAverification and IXIA, SmartBit debugging experience are a plus.
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-11-27 13:41:05
楼主
发表于 2013-12-5 10:17:31
