小弟又有几篇文章,需要求助各位了,谢谢!1: An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
2: A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs
3: A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC
4: A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
5: Multi-step capacitor-splitting SAR ADC
6: A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
7: A 187.5Vrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC